
Chapter 4 – SocketModem Parallel Interface – A Programmer’s Description
LSR Line Status
Bit 7: Error in RX FIFO. This bit is always set to 1 if at least one data byte in the RX FIFO has an error. This will clear when there are no more errors in the RX FIFO.
Bit 6: Transmitter empty. This bit is the same as LSR bit 5 (THRE) in MMM
Bit 5: Transmitter holding register empty. This bit is set to 1 when either the transmitter holding register has been read (emptied) by the
Bits
Bit 1: Overrun error. This bit is set if the
Bit 0: Data ready bit. This bit is set to 1 when received data is available, either in the RX FIFO (16550 mode) or the RBR (16450 mode). This bit is set immediately upon the
MSR Modem Status
Bits 4 through 7 of the MSR can also take on the MCR bits 0 through 3 value when in MCR loop mode (i.e. when MCR b4 = 1). The transfer of bits in loop back has a null modem twist (i.e. MCR b0 goes to MSR b5 and MCR b1goes to MSR b4).
Bit 7: Data carrier detect (DCD) bit.
Bit 6: Ring indicator (RI) bit.
Bit 5: Data set ready (DSR) bit.
Bit 4: Clear to send (CTS) bit.
Bit 3: Delta data carrier detect pin. This bit is set to a 1 whenever the data carrier detect bit changes state. It is reset when the host reads the modem status register.
Bit 2: Trailing edge ring indicator bit. This bit is set to 1 on the falling edge of the ring indicator bit. It is reset when the host reads the modem status register.
Bit 1: Delta data set ready bit. This bit is set to 1 whenever the data set ready changes state. It is reset when the host reads the modem status register.
Bit 0: Delta clear to send bit. This bit is a one whenever the clear to send bit changes state. It is reset when the host reads the modem status register.
SocketModem Global MT5634SMI Developer’s Guide | 21 |