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| EM78P458/459 | ||
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| OTP ROM | ||
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Table 4 Usage of Port 6 Input Changed | ||||||
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| Usage of Port 6 Input Status Changed |
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| (I) | (II) Port 6 Input Status Change Interrupt |
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| (a) Before SLEEP | 1. | Read I/O Port 6 (MOV R6,R6) |
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| 1. | Disable WDT | 2. | Execute "ENI" |
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| 2. | Read I/O Port 6 (MOV R6,R6) | 3. | Enable interrupt (Set IOCF0.1) |
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| 3. | Execute "ENI" or "DISI" | 4. | IF Port 6 changed (interrupt) |
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| 4. | Enable interrupt (Set IOCF0.1) |
| → Interrupt vector (008H) |
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| 5. | Execute "SLEP" instruction |
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| (b) After |
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| 1. | IF "ENI" → Interrupt vector (008H) |
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| 2. | IF "DISI" → Next instruction |
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4.5 RESET and Wake-up
1. The function of RESET and Wake-up
A RESET is initiated by one of the following events-
(1)
(2)/RESET pin input "low", or
(3)WDT
The device is kept in a RESET condition for a period of approximately 18ms (one oscillator
•The oscillator is running, or will be started.
•The Program Counter (R2) is set to all "0".
•All I/O port pins are configured as input mode
•The Watchdog Timer and prescaler are cleared.
•When power is switched on, the upper 3 bits of R3 are cleared.
•The bits of the CONT register are set to all "1" except for the Bit 6 (INT flag).
•The bits of the IOCB0 register are set to all "1".
•The IOCC0 register is cleared.
•The bits of the IOCD0 register are set to all "1".
•Bit 7 of the IOCE0 register is set to "1", and Bit 6 is cleared.
•Bits 0~6 of RF register and bits 0~6 of IOCF0 register are cleared.
Executing the “SLEP” instruction will assert the sleep (power down) mode. While entering sleep mode, the WDT (if enabled) is cleared but keeps on running. The controller can be awakened by-
This specification is subject to change without prior notice. | 26 | 07.01.2003 (V1.3) |