ELAN Home Systems EM78P459AK, EM78P459AM, EM78P458AM, EM78P458AP manual Add A,R

Page 54

 

 

 

 

 

 

 

 

EM78P458/459

 

 

 

 

 

 

 

 

 

OTP ROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INSTRUCTION BINARY

HEX

MNEMONIC

OPERATION

 

STATUS AFFECTED

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0011

10rr

rrrr

03rr

ADD A,R

A + R A

 

Z,C,DC

 

 

0

0011

11rr

rrrr

03rr

ADD R,A

A + R R

 

Z,C,DC

 

 

0

0100

00rr

rrrr

04rr

MOV A,R

R A

 

Z

 

 

0

0100

01rr

rrrr

04rr

MOV R,R

R R

 

Z

 

 

0

0100

10rr

rrrr

04rr

COMA R

/R A

 

Z

 

 

0

0100

11rr

rrrr

04rr

COM R

/R R

 

Z

 

 

0

0101

00rr

rrrr

05rr

INCA R

R+1 A

 

Z

 

 

0

0101

01rr

rrrr

05rr

INC R

R+1 R

 

Z

 

 

0

0101

10rr

rrrr

05rr

DJZA R

R-1 A, skip if zero

 

None

 

 

0

0101

11rr

rrrr

05rr

DJZ R

R-1 R, skip if zero

 

None

 

 

0

0110

00rr

rrrr

06rr

RRCA R

R(n) A(n-1),

 

C

 

 

R(0) C, C A(7)

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0110

01rr

rrrr

06rr

RRC R

R(n) R(n-1),

 

C

 

 

R(0) C, C R(7)

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0110

10rr

rrrr

06rr

RLCA R

R(n) A(n+1),

 

C

 

 

R(7) C, C A(0)

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0110

11rr

rrrr

06rr

RLC R

R(n) R(n+1),

 

C

 

 

R(7) C, C R(0)

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0111

00rr

rrrr

07rr

SWAPA R

R(0-3) A(4-7),

 

None

 

 

R(4-7) A(0-3)

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0111

01rr

rrrr

07rr

SWAP R

R(0-3) R(4-7)

 

None

 

 

0

0111

10rr

rrrr

07rr

JZA R

R+1 A, skip if zero

 

None

 

 

0

0111

11rr

rrrr

07rr

JZ R

R+1 R, skip if zero

 

None

 

 

0

100b

bbrr

rrrr

0xxx

BC R,b

0 R(b)

 

None <Note2>

 

 

0

101b

bbrr

rrrr

0xxx

BS R,b

1 R(b)

 

None <Note3>

 

 

0

110b

bbrr

rrrr

0xxx

JBC R,b

if R(b)=0, skip

 

None

 

 

0

111b

bbrr

rrrr

0xxx

JBS R,b

if R(b)=1, skip

 

None

 

 

1

00kk kkkk kkkk

1kkk

CALL k

PC+1 [SP],

 

None

 

 

(Page, k) PC

 

 

 

 

 

 

 

 

 

 

 

 

 

1

01kk kkkk kkkk

1kkk

JMP k

(Page, k) PC

 

None

 

 

1

1000

kkkk kkkk

18kk

MOV A,k

k A

 

None

 

 

1

1001

kkkk kkkk

19kk

OR A,k

A k A

 

Z

 

 

1

1010

kkkk kkkk

1Akk

AND A,k

A & k A

 

Z

 

 

1

1011

kkkk kkkk

1Bkk

XOR A,k

A k A

 

Z

 

 

1

1100

kkkk kkkk

1Ckk

RETL k

k A,

 

None

 

 

[Top of Stack] PC

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1101

kkkk kkkk

1Dkk

SUB A,k

k-A A

 

Z,C,DC

 

 

1

1110

0000 0001

1E01

INT

PC+1 [SP],

 

None

 

 

001H PC

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1111

kkkk kkkk

1Fkk

ADD A,k

k+A A

 

Z,C,DC

 

 

0

0000

0010 0000

0020

TBL

R2+A R2

 

Z,C,DC

 

 

Bits 8~9 of R2 unchanged

 

 

 

 

 

 

 

 

 

 

 

 

<Note 1> This instruction is applicable to IOC50~IOC60, IOC90~IOCF0, IOC51~IOCF1 only. <Note 2> This instruction is not recommended for RF operation.

<Note 3> This instruction cannot operate under RF.

This specification is subject to change without prior notice.

54

07.01.2003 (V1.3)

Image 54
Contents EM78P458/459 BIT MICRO-CONTROLLEREM78P458/459 Application NoteGeneral Description Features EM78P458/459 PIN Assignment EM78P459 Pin Description R0 Indirect Addressing Register Function DescriptionOperational Registers R1 Time Clock /CounterProgram Counter Organization R5 ~ R6 Port 5 ~ Port R3 Status RegisterR4 RAM Select Register R7 ~ R8Data Memory Configuration 10. RB R9 Adcon Analog to Digital ControlRA Addata the converted value of ADC 11. RCRF Interrupt Status Register Special Purpose Registers13. RE 15. R10 ~ R3FInte INT PAB PSR2 PSR1 PSR0 Control RegisterIOC50 ~ IOC60 I/O Port Control Register Bit 0 PSR0 ~ Bit 2 PSR2 TCC/WDT prescaler bitsIOC90 Gcon I/O Configuration & Control of ADC OP2E OP1EVrefs COE IMS2 IMS1 IMS0 CKR1 CKR0 Bit4Bit2 IMS2IMS0 Description of AD Configuration Control BitsIOCB0 Pull-down Control Register IMS2IMS0IOCC0 Open-Drain Control Register IOCD0 Pull-high Control RegisterWdte EIS IOCE0 WDT Control RegisterIOCF0 Interrupt Mask Register Cmpie PWM2IE PWM1IE Adie Exie Icie TcieIOC51 Pwmcon PWM2E PWM1E T2EN T1ENBit 5Bit 3 VOF12VOF10 Offset voltage bits IOC81 PRD1 Period of PWM1CALI1 SIGN1 CALI2 SIGN2IOCB1 PRD2 Period of PWM2 Bit 5Bit 3 VOF22VOF20 Offset voltage bitsTCC/WDT & Prescaler Block Diagram of TCC and WDT I/O PortsCcircuit of I/O Port and I/O Control Register for Port Circuit of I/O Port and I/O Control Register for P60~P67 Reset and Wake-up Function of Reset and Wake-upUsage of Port 6 Input Changed Wake-up/Interrupt Function Contw CLR R1 Status of T, and P of Status Register Values of RST, T, and P after Reset Status of RST, T and P being Affected by EventsInterrupt Analog-To-Digital Converter ADC Interrupt Input CircuitADC Control Register ADCON/R9, AD-CMP-CON/IOCA0, GCON/IOC90 BIT Symbol Iocs Adrun Adpd ADIS2 ADIS1 ADIS0BIT Symbol Vrefs COE IMS2 IMS1 IMS0 CKR1 CKR0 ADCON/R9GCON/IOC90 ADC Data Register ADDATA/RACKR1 and CKR0 Bit 1 and Bit 0 The conversion time select Shows the Gains and the Operating Range of ADCD Conversion Time D Operation During Sleep ModeD Sampling Time Programming Steps/ConsiderationsDemonstration Programs CINT== 0XFIocs Adrun Adpd ADIS2 ADIS1 ADIS0 Dual Sets of PWM Pulse Width Modulation OverviewIncrement Timer Counter Tmrx TMR1H/TWR1L or TMR2H/TWR2L Functional Block Diagram of the Dual PWMsComparator PWM Programming Procedures/StepsPWM Period Prdx PRD1 or PRD2 Period = Prdx + 1 * 4 * 1/Fosc * Tmrx prescale valueTMR1X and TMR2X TMR1H/TWR1L and TMR2H/TMR2L TimerFunction description Prdx PRD1 and PRD2 PWM period registerComparator Timer programming procedures/stepsExternal Reference Signal Programming the Related RegistersUsing as An Operation Amplifier Wake-up from Sleep ModeInterrupt Initialized Values after Reset Summary of the Initialized Values for RegistersCALI1 SIGN1 Oscillator Oscillator ModesEM78P458 Crystal Oscillator/Ceramic Resonators XtalSummary of Maximum Operating Speeds EM78P459EM78P458 EM78P459 HXTLXT VddExternal RC Oscillator Mode RC Oscillator Mode with Internal Capacitor EM78P458 EM78P459 Vcc RextResidue-Voltage Protection Power-on ConsiderationsExternal Power on Reset Circuit EM78P458 EM78P459 Rin Code Option Register Word Enwdt Clks PTB HLF RCT HLPBit 5 ~ Bit 0 ID5~ID0 Customer’s ID Bit 11 ~ Bit 9 VOF22~VOF20 Offset voltage bitsInstruction Set List of the instruction set of EM78P458/459ADD A,R AC Test Input/Output Waveform Timing DiagramsReset Timing CLK=0 TCC Input Timing CLKS=0Absolute Maximum Ratings Electrical Characteristics Crystal type, two clocksComparatorOP CharacteristicVdd = 5.0V,Vss=0V,Ta=0 to AC Electrical CharacteristicTa=0C ~ 70 C, VDD=5V±5%, VSS=0VIVR OTP MCU AppendixPackage Types DIP