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| Freescale Semiconductor, Inc. | |||
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| Operating Instructions | ||
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| TABLE | ||||
| Reg. | Device Type |
| Bus | Init Value | Description |
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| BR5 | PM5350 - ATM UNI |
| Buffered | 14600801 | Base at 14600000, 8 bit port size, no parity, GPCM |
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| PPC |
| on PPC bus. |
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| OR5 |
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| FFFF8E36 | 32K Byte block size, delayed CS assertion, early |
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| CS and WE negation for write cycle, relaxed |
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| timing, 7 w.s. for read, 8 for write, extended hold |
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| time after read. |
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| BR6 | User’s peripheral |
| Buffered | - | - |
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| PPC |
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| OR6 |
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| - | - | |
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| BR7 | User’s peripheral |
| Buffered | - | - |
Inc. |
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| PPC |
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OR7 |
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| - | - | ||
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BR10 | DSPRAM |
| Local PPC | 020000C1 | Base at 200000, 64 bit port size, no parity,UPMC | |
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Semiconductor, | OR10 |
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| FFF80000 | 512K Byte block size |
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BR11 | DSP Peripherals |
| Local PPC | 01F00021 | Base at 1F00000, 64 bit port size, no parity, GPCM | |
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| on local PPC bus. |
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| OR11 |
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| FFFF0000 | 64K Byte block size |
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| PSDMR | SDRAM 64bit |
| C26B36A3 | Page interleaving, Refresh enabled, normal | |
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| PPC | (C2692452) | operation, address muxing mode SDAM=2, A(15- |
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| 17) on BNKSEL(0:2), A8 on PSDA10, 8(4) clocks |
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| refresh recovery, 3(2) clocks precharge to activate |
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| delay, 3(2) clocks activate to read/write delay, 4 |
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| beat burst length, 2(1) clock last data out to |
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| precharge, 2(1) clock write recovery time, Internal |
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| address muxing, normal timing, 3(2) clocks CAS |
Freescale |
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| latency. |
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| SDRAM 32bit |
| C28737A3 | Page interleaving, Refresh enabled, normal | ||
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| PPC with | (C2432552) | operation, address muxing mode 1, |
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| Host support |
| BNKSEL(0:2), A9 on PSDA10, 8(4) clocks refresh |
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| recovery, 3(2) clocks precharge to activate delay, |
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| 3(2) clocks activate to read/write delay, 8 beat |
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| burst length, 2(1) clock last data out to precharge, |
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| 2(1) clock write recovery time, Internal address |
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| muxing, normal timing, 3(2) clocks CAS latency. |
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| PSRT | SDRAM Supported |
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| 22 | Generates refresh every 14 ∝sec, while 15.6 ∝sec |
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| required. Therefore is refresh redundancy of 6.6 |
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| msec throughout full SDRAM refresh cycle which |
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| All PPC Bus |
| completes in 64 msec. I.e., Application s/w may |
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| Config. |
| withhold the bus upto app. 6.6 msec in a 57.3 |
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| msec period, without jeopardizing the contents of |
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| the PPC bus SDRAM. |
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| MPTPR | SDRAM Supported |
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| 2800(1300) | Divide Bus clock by 40D (20D) |
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MOTOROLA | MSC8101ADS RevB User’s Manual | 37 |
For More Information On This Product,
Go to: www.freescale.com