Nortel Networks MSC8101 ADS user manual SPICLKPD18, SPIMOSIPD17, Hwrds, PD7, Atrckdis, Hostpd

Page 84

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

TABLE B1-3. P2 - CPM Expansion - Interconnect Signals

Pin No.

Signal Name

Attribute

Description

 

 

 

 

 

 

 

 

A13

SPISELb(PD19)

I/O, T.S.

When SPI port is enabled, this signal is the select input line for

 

 

 

that port. When this port is disabled, this signal may be used to

 

 

 

any available alternate function for PD19. In fact, for the ADS

 

 

 

application using as GPIO output pin.

 

 

 

 

A14

SPICLK(PD18)

I/O, T.S.

When SPI port is enabled, this signal is SPI clock output line for

 

 

 

that port. When this port is disabled, this signal may be used to

 

 

 

any available alternate function for PD18.

 

 

 

 

A15

SPIMOSI(PD17)

I/O, T.S.

When SPI port is enabled, this signal is master output line for that

 

 

 

port. When this port is disabled, this signal may be used to any

 

 

 

available alternate function for PD17.

 

 

 

 

A16-A20

N.C.

-

Not connected

 

 

 

 

A21

HCS2

I

Chip-select 2 input for HDI16 port. Present as well as at P4

 

 

 

connector.

 

 

 

 

A22

HCS1

I

Chip-select 1 input for HDI16 port. Present as well as at P4

 

 

 

connector.

 

 

 

 

A23

HRDRW

I

When the HDI16 is programmed to interface to a single data

 

 

 

strobe host bus, this pin is the read/write input (HRW). When the

 

 

 

HDI16 is programmed to interface to a double data strobe host

 

 

 

bus, this pin is the read data strobe Schmitt trigger input (HRD).

 

 

 

Present as well as at P4 connector.

 

 

 

 

A24

HWRDS

I

When the HDI16 is programmed to interface to a single data

 

 

 

strobe host bus, this pin is the data strobe Schmitt trigger input

 

 

 

(HDS). When the HDI16 is programmed to interface to a double

 

 

 

data strobe host bus, this pin is the write data strobe Schmitt

 

 

 

trigger input (HWR). Present as well as at P4 connector.

 

 

 

 

A25

PD7

 

MSC8101’s Port D7 Parallel I/O line. May be used to any of its

 

 

 

available functions

 

 

 

 

A26-A28

N.C.

-

Not connected

 

 

 

 

A29

ATRCKDIS

I

ATM Receive Clock Out Disable. When active (H), the ATMRCLK

 

 

 

output, on pin C29 of this connector, is Tri-stated. When either not

 

 

 

connected or driven low, ATMRCLK on pin C29, is enabled. This

 

 

 

provides compatibility with ENG revision of T/ECOM

 

 

 

communication tools.

 

 

 

 

A30

HOSTPD

I

Host tool present detect. Disable Host Interface with active low

 

 

 

(GND) for not compatible external tools.

 

 

 

 

A31-A32

5V

P

5V Supply. Connected to ADS’s 5V VCC plane. Provided as

 

 

 

power supply for external tool. For allowed current draw, see

 

 

 

TABLE 7-1."Off-Board Application Maximum Current

 

 

 

Consumption" on page 66.

 

 

 

 

B1

ATMTXENb (PA31)

I/O, T.S.

ATM Transmit Enabled (L). When this signal is asserted (Low),

 

 

 

while the ATM port is enabled and ATMTFCLK is rising, an octet

 

 

 

of data, ATMTXD(7:0), is written into the transmit FIFO of the

 

 

 

PM5350. When the ATM port is disabled, this line may be used

 

 

 

for any available function of PA31.

 

 

 

 

MOTOROLA

MSC8101ADS RevB User’s Manual

B-83

For More Information On This Product,

Go to: www.freescale.com

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Contents MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Introduction Abbreviations’ ListRelated Documentation Specification MSC8101ADS SpecificationsCharacteristics Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting The Core Supply Voltage Level Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9Setting HReset Configuration Source OnCE Connection Scheme Host I/F OperationStand Alone Operation Host System Debug Scheme B34 +5V Power Supply Connection JTAG/OnCE Connector P6Host I/F Connector P4 P6 JTAG/OnCE Port ConnectorP4 Host I/F Connector Terminal to MSC8101ADS RS-232 ConnectionFlash Memory Simm Installation 38 10/100-Base-T Ethernet Port ConnectionFlash Memory Simm Insertion Host I/F Setting SW1 Emulator Enable EE SW2Abort Switch SW3 Soft Reset Sreset Switch SW4Data Bus Width Setting SW5 & SW6 Hard Reset Hreset Switch SW7 Power-On Reset Switch Preset SW8Configuration Switch SW9 Available Clock Mode Setting Boot Mode Select SW10Modck CPMSoftware Options Switch SW11 431 JP1 DLL DisableJumpers 432 JP2 Clock Buffer Set433 JP3 50 Ohm Enable 436 JP6,JP7 MIC Enable437 JP9 5V power supply for Codec 434 JP4 VPP Source SelectorLEDs Ethernet Link Indicator LD4 Fast Ethernet Clsn Indicator LD5ATM RX Indicator LD6 ATM TX Indicator LD7MSC8101’s Registers’ Programming SIU Registers’ Programming System InitializationMemory Controller Registers Programming Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Reset & Reset Configuration Power- On ResetPower On Reset Configuration Manual Hard ResetSummary Reset Configuration Schemes Hard Reset Configuration WordManual Soft Reset IRQ2Local Interrupter Clock GeneratorBus Buffering Chip Select GeneratorSynchronous Dram Bank MSC8101ADS Chip Select Assignments Bus Timing MachineMHz Sdram Mode Register Programming Sdram ProgrammingSdram Cycle Type \ Flash Delay nsec Flash Memory SimmSdram Refresh Flash Simm Connection Scheme Flash Programming VoltageCommunication Ports Ports Function Enable MSC8101 I/O Ports/Name581 ATM Port 582 100/10 Base T PortCS4221 Programming Audio Codec5831 CS4221 Programming CS4221 Programming 584 T1/E1 Ports585 RS232 Ports Host I/F Host I/F Interconnect signals DMA off-board toolBoard Control & Status Register Bcsr BCSR0 Description BCSR0 Board Control / Status RegisterBIT Mnemonic PON ATT DEF HostcspBCSR0 Description 10. BCSR1 DescriptionBCSR1 Board Control / Status Register 10. BCSR1 Description PON ATT DEF AtmrstFethien Fethrst11. Peripheral’s Availability Decoding 12. BCSR2 DescriptionBCSR2 Board Control / Status Register 12. BCSR2 Description 13. Flash Presence Detect 75 Encoding14. Flash Presence Detect 41 Encoding BCSR3 Board Status Register15. BCSR3 Description 16. EXTOOLI03 Assignment 17. External Tool Revision Encoding18. ADS Revision Encoding EngineeringPPC Bus Memory Map MSC8101ADS Memory Map MSC8101ADS Memory Map FE000000 FfffffffFF000000 Ffffffff FF800000 FfffffffPower rails ADS Power SchemeOff-Board Application Maximum Current Consumption 711 5V Bus712 3V Bus 713 5V BusAppendix a MSC8101 Bill of Material A1 BOM Table A-1. MSC8101ADS Bill Of MaterialFreescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information Interconnect Signals B11Table B1-2. P1 System Expansion Interconnect Signals GND TSTAT0TSTAT1 TSTAT2 TSTAT3 TSTAT4 TSTAT5Clkx Damage to the PM5350 ATM UNIEXPD0 EXPD1EXPD2 EXPD3EXPCTL0 Table B1-3. P2 CPM Expansion Interconnect Signals B12 MSC8101ADS’s P2 CPM Expansion ConnectorSCC1RXD PD30 SPICLKPD18 SPIMOSIPD17Hwrds PD7Atmtsoc PA29 Atmrsoc PA27Atmrfclk Atmrca PA26ATMRXD7 PA17 ATMRXD6 PA16ATMRXD5 PA15 ATMRXD4 PA14Fethtxen PB29 Fethrxer PB28Fethcol PB27 Fethcrs PB26HD0 HD1HD2 HD3Atmfclk PC26 Fethmdc PC13Fethmdio PC12 PC7PC6 SMCTX1PC5Table B1-4. P3 ISP Connector Interconnect Signals B14 P4 Host Interface ConnectorB13 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HA1 HA2 HA3 HCS1Hack HreqTable B1-6. P6 JTAG/ONCE Connector Interconnect Signals B15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer ConnectorsB16 HDSTable B1-7. P12 Ethernet Port Interconnect Signals B17 P12 Ethernet Port ConnectorB18 P15,P16 SMB Connectors B19 P17,P18 Double RJ45 T1/E1 Line ConnectorsB110 P19,P21,P24 Stereo Phone Jack Connectors B111 P20,P22,P23,P25 RCA Jack ConnectorsTable B1-10. P27A Interconnect Signals Table B1-11. P27B Interconnect SignalsB112 P26 5V Power Supply Connectors B113 P27A,B RS232 Ports’ ConnectorsFreescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc Logic Equations C11 First Include FileC12 Second Include file C13 Main File Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0 Constant EE45HOLDVALUEConstant SIZE1 ConstantConstant TCPCDEFAULT0 Constant TCPCDEFAULT1 HDIMDEN~ Host SW Enable RSTCNF~ OutputSRESET~ HRESET~ BidirSBOOTENOUT~ SPARE1 OutputHDIEN~ HRRQEN~WDTIMER1 WDTIMER2WDTIMER3 WDTIMER4Eepromenable Resets CleartowdctrlBCSR1 SBOOTEN~ Scndcfgbyteread Thirdcfgbyteread FourthcfgbytereadBCSR3 IRQ0BCSR1PONDEF0..SIZE1 BCSR3PONDEF0..SIZE3Begin Defaults END DefaultsBCSR0 BCSR0PONCONST0..5 EEDPONDEFAULT,RSV37PONDEFAULT ElseEND if END Generate EE Pins Regularpoweronreset = RPORI~ == RegularponresetactivePSDVAL~ = Opndrnvcc END ifIf Hdds then If !HDSP then Hdiwr =Else Hdiwr = END if ElseElsif MPCWRITEBCSR1 then Elsif MPCWRITEBCSR4 thenElsif MPCWRITEBCSR5 then Elsif MPCWRITEBCSR6 thenSIGNALLAMP1~ Elsif MPCREADBCSR1 then If MPCREADBCSR0 thenElsif MPCREADBCSR3 then HRESET~ = SRESET~ =Elsif Firstcfgbyteread then Elsif Scndcfgbyteread thenThen SIGLAMP0OUT~ = GND Else Then SIGLAMP1OUT~Else SIGLAMP1OUT~ END if If !T1234EN~ & FETHIEN~ then116 END if Drive Poreset Impulse Reconfig Using BCSR4 Watchdog for Auto ReconfigurationMODCK1-3 Driven 118
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