Nortel Networks MSC8101 ADS user manual Table B1-4. P3 ISP Connector Interconnect Signals, B13

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

B•1•3

P3 - Altera’s In System Programming (ISP)

This is a 10 pin generic 0.100" pitch header connector, providing In System Programming capabil- ity for Altera CPLD devices made programmable logic on board. The pinout of P3 is shown in TABLE B1-4. "P3 - ISP Connector - Interconnect Signals" below:

TABLE B1-4. P3 - ISP Connector - Interconnect Signals

Pin No.	Signal Name	Attribute	Description


1	TCK	I	ISP Test port Clock. This clock shifts in / out data to / from the
			programmable logic JTAG chain.

2	GND	P	Digital GND. Main GND plane.

3	TDO	O	ISP Transmit Data Output. This the prog. logic’s JTAG serial data
			output driven by Falling edge of TCK.

4	VCC	P	Connect to 3.3V power supply bus for feeding an external
			programmer logic.

5	TMS	I	ISP Test Mode Select. This signal qualified with TCK, changes
			the state of the prog. logic JTAG machine.

6	N.C.	-	Not Connected.

7	N.C.	-	Not Connected.

8	N.C.	-	Not Connected.

9	TDI	I	ISP Transmit Data In. This is the prog. logic’s JTAG serial data
			input, sampled by the MCS8101 on the rising edge of TCK.

10	GND	P	Digital GND. Main GND plane.

B•1•4	P4 - Host Interface Connector

This is a 36 pin two rows 0.100" pitch header connector. For more user’s convenience each of the Host Interface signals is present at the CPM The pinout of P4 is shown in TABLE B1-5. "P4 - Host Interface Connector - Interconnect Signals" below:

TABLE B1-5. P4 - Host Interface Connector - Interconnect Signals

Pin No.	Signal Name	Attribute	Description


1	GND	P	Digital GND. Main GND plane.

2

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MSC8101ADS RevB User’s Manual

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Contents MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Abbreviations’ List IntroductionRelated Documentation MSC8101ADS Specifications SpecificationCharacteristics Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9 Setting The Core Supply Voltage LevelSetting HReset Configuration Source Host I/F Operation OnCE Connection SchemeHost System Debug Scheme B Stand Alone OperationJTAG/OnCE Connector P6 34 +5V Power Supply ConnectionP6 JTAG/OnCE Port Connector Host I/F Connector P4Terminal to MSC8101ADS RS-232 Connection P4 Host I/F Connector38 10/100-Base-T Ethernet Port Connection Flash Memory Simm InstallationFlash Memory Simm Insertion Emulator Enable EE SW2 Host I/F Setting SW1Soft Reset Sreset Switch SW4 Abort Switch SW3Data Bus Width Setting SW5 & SW6 Power-On Reset Switch Preset SW8 Hard Reset Hreset Switch SW7Configuration Switch SW9 CPM Available Clock Mode SettingBoot Mode Select SW10 Modck432 JP2 Clock Buffer Set Software Options Switch SW11431 JP1 DLL Disable Jumpers434 JP4 VPP Source Selector 433 JP3 50 Ohm Enable436 JP6,JP7 MIC Enable 437 JP9 5V power supply for CodecLEDs ATM TX Indicator LD7 Ethernet Link Indicator LD4Fast Ethernet Clsn Indicator LD5 ATM RX Indicator LD6MSC8101’s Registers’ Programming System Initialization SIU Registers’ ProgrammingMemory Controller Registers Programming Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Manual Hard Reset Reset & Reset ConfigurationPower- On Reset Power On Reset ConfigurationHard Reset Configuration Word Summary Reset Configuration SchemesIRQ2 Manual Soft ResetClock Generator Local InterrupterChip Select Generator Bus BufferingMSC8101ADS Chip Select Assignments Bus Timing Machine Synchronous Dram BankSdram Programming MHz Sdram Mode Register ProgrammingSdram Flash Memory Simm Cycle Type \ Flash Delay nsecSdram Refresh Flash Programming Voltage Flash Simm Connection SchemeCommunication Ports MSC8101 I/O Ports/Name Ports Function Enable582 100/10 Base T Port 581 ATM PortAudio Codec CS4221 Programming5831 CS4221 Programming 584 T1/E1 Ports CS4221 Programming585 RS232 Ports Host I/F DMA off-board tool Host I/F Interconnect signalsBoard Control & Status Register Bcsr PON ATT DEF Hostcsp BCSR0 DescriptionBCSR0 Board Control / Status Register BIT Mnemonic10. BCSR1 Description BCSR0 DescriptionBCSR1 Board Control / Status Register Fethrst 10. BCSR1 DescriptionPON ATT DEF Atmrst Fethien12. BCSR2 Description 11. Peripheral’s Availability DecodingBCSR2 Board Control / Status Register BCSR3 Board Status Register 12. BCSR2 Description13. Flash Presence Detect 75 Encoding 14. Flash Presence Detect 41 Encoding15. BCSR3 Description Engineering 16. EXTOOLI03 Assignment17. External Tool Revision Encoding 18. ADS Revision EncodingPPC Bus Memory Map MSC8101ADS Memory Map FF800000 Ffffffff MSC8101ADS Memory MapFE000000 Ffffffff FF000000 FfffffffADS Power Scheme Power rails713 5V Bus Off-Board Application Maximum Current Consumption711 5V Bus 712 3V BusAppendix a MSC8101 Bill of Material Table A-1. MSC8101ADS Bill Of Material A1 BOMFreescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information B11 Interconnect SignalsTable B1-2. P1 System Expansion Interconnect Signals TSTAT2 TSTAT3 TSTAT4 TSTAT5 GNDTSTAT0 TSTAT1Damage to the PM5350 ATM UNI ClkxEXPD3 EXPD0EXPD1 EXPD2EXPCTL0 B12 MSC8101ADS’s P2 CPM Expansion Connector Table B1-3. P2 CPM Expansion Interconnect SignalsSCC1RXD PD30 PD7 SPICLKPD18SPIMOSIPD17 HwrdsAtmrca PA26 Atmtsoc PA29Atmrsoc PA27 AtmrfclkATMRXD4 PA14 ATMRXD7 PA17ATMRXD6 PA16 ATMRXD5 PA15Fethcrs PB26 Fethtxen PB29Fethrxer PB28 Fethcol PB27HD3 HD0HD1 HD2Fethmdc PC13 Atmfclk PC26SMCTX1PC5 Fethmdio PC12PC7 PC6B14 P4 Host Interface Connector Table B1-4. P3 ISP Connector Interconnect SignalsB13 Hreq HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9HA1 HA2 HA3 HCS1 HackHDS Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors B16B19 P17,P18 Double RJ45 T1/E1 Line Connectors Table B1-7. P12 Ethernet Port Interconnect SignalsB17 P12 Ethernet Port Connector B18 P15,P16 SMB ConnectorsB111 P20,P22,P23,P25 RCA Jack Connectors B110 P19,P21,P24 Stereo Phone Jack ConnectorsB113 P27A,B RS232 Ports’ Connectors Table B1-10. P27A Interconnect SignalsTable B1-11. P27B Interconnect Signals B112 P26 5V Power Supply ConnectorsFreescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc C11 First Include File Logic EquationsC12 Second Include file C13 Main File Constant Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant EE45HOLDVALUE Constant SIZE1HRESET~ Bidir Constant TCPCDEFAULT0 Constant TCPCDEFAULT1HDIMDEN~ Host SW Enable RSTCNF~ Output SRESET~HRRQEN~ SBOOTENOUT~SPARE1 Output HDIEN~WDTIMER4 WDTIMER1WDTIMER2 WDTIMER3Scndcfgbyteread Thirdcfgbyteread Fourthcfgbyteread EepromenableResets Cleartowdctrl BCSR1 SBOOTEN~BCSR3PONDEF0..SIZE3 BCSR3IRQ0 BCSR1PONDEF0..SIZE1END Defaults Begin DefaultsBCSR0 BCSR0PONCONST0..5 Else EEDPONDEFAULT,RSV37PONDEFAULTEND if END Generate END if EE PinsRegularpoweronreset = RPORI~ == Regularponresetactive PSDVAL~ = OpndrnvccEND if Else If Hdds thenIf !HDSP then Hdiwr = Else Hdiwr =Elsif MPCWRITEBCSR6 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR5 thenIf MPCREADBCSR0 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenElsif MPCREADBCSR3 then Elsif Scndcfgbyteread then HRESET~ =SRESET~ = Elsif Firstcfgbyteread thenEND if If !T1234EN~ & FETHIEN~ then Then SIGLAMP0OUT~ = GND ElseThen SIGLAMP1OUT~ Else SIGLAMP1OUT~116 Watchdog for Auto Reconfiguration END if Drive Poreset Impulse Reconfig Using BCSR4MODCK1-3 Driven 118