Nortel Networks MSC8101 ADS user manual ATM Port, 582 100/10 Base T Port

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Freescale Semiconductor, Inc.

 

 

Freescale Semiconductor, Inc.

 

 

 

 

 

Functional Description

 

 

 

 

 

 

 

TABLE 5-6. Ports Function Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADS On-Board Peripherals

 

 

DMA Ext.

Possible

 

 

 

 

 

 

 

Tool

Collision

 

 

 

 

 

 

 

 

 

 

MSC8101 I/O Ports/Name

 

 

 

 

 

 

 

 

 

QFALC on

 

CODEC

Fast Et

ATM8

 

 

 

 

 

T1/E1

T1/E1

T1/E1

T1/E1

on

on

on

-

-

 

 

 

TDMA1

FCC2

FCC1

 

 

 

 

 

TDMA1

TDMB2

TDMC2

TDMD2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PC30/TDMA1-TXCLK(CLK2)

 

 

 

 

 

 

 

 

+

 

PC31/TDMA1-RXCLK(CLK1)

 

+

 

 

 

+

 

 

+

 

PD30/IDMA2-DRACK/IDMA2-DONE

 

 

 

 

 

 

 

 

+

 

PD31/IDMA1-DRACK/IDMA1-DONE

 

 

 

 

 

 

 

 

+

 

5•8•1

ATM Port

 

 

 

 

 

 

 

 

 

 

To support the MSC8101 ATM controller, a 155.52Mbps User Network Interface (UNI) is provided on board, connected to FCC1 of the MSC8101 via UTOPIA I/F.Use is done with PM5350 S/UNI- 155-ULTRA by PMC-SIERA. Although these transceivers are capable of supporting 51.84Mbps rate, support is given only to the higher rate.

The control over the transceiver is done using the microprocessor i/f of the transceiver, controlled by the MSC8101 memory controller’s GPCM. Since the UNI is 5V powered and the MSC8101 3.3V powered (5V intolerant), the UNI is buffered (LCX buffers) from the MSC8101 on both the receive part of UTOPIA I/F and MP control ports.

The ATM transceiver may enabled / disabled at any time by writing ’0’ / ’1’ to the ATMEN~ bit in BCSR1/2. When ATMEN~ is negated, (’1’) the MPcontrol port is also detached from the MSC8101 and its associated FCC1 may be used off-board via the expansion connectors.

The ATM transceiver reset input is driven by HRESET~ signal of the MSC8101, so that the UNI is reset whenever a hard-reset sequence occurs. The UNI may also be reset by either asserting ATM_RST bit in BCSR1/3 or by asserting (’1’) the RESET bit in the Master Reset and Identify / Load Meters register via the UNI MP I/F.

The UNI transmit and receive clocks is fed with a 19.44 MHz +/- 20 ppm, clock generator, 5 V powered, while the receive and transmit FIFOs’ clock is provided by the MSC8101, optionally from the same clock or separate clocks, hard-configured.

The ATM SAR is connected to the physical medium by an optical I/F. Use is done with HP’s HFBR 5205 optical I/F, which operates at 1300 nm with upto 2 Km transmission range.

5•8•2 100/10 Base - T Port

A Fast Ethernet port with T.P. (100-Base-TX) I/F is provided on the MSC8101ADS. This port is also support 10 Mbps ethernet (10-Base-T) via the same transceiver - the LXT970 by Level One.

The LXT970 is connected to FCC2 of the MSC8101 via MII interface, which is used for both - device’s control and data path. The initial configuration of the LXT970 is done be setting desired values at 8 configuration signals: FDE, CFG(0:1) and MF(0:4). The MF(0:4) pins however, are con- trolled by 4 - voltage levels, this to allow each pin to configure two functions. On the MSC8101ADS these pins is driven by factory set 0Ω resistors, connected to a voltage divider, allowing future option change during production.

The LXT970 reset input is driven by HRESET~ signal of the MSC8101, resetting the transceiver whenever hard-reset sequence is taken. The LXT970 may also be reset by either asserting the FETH_RST bit in BCSR1/5 or by asserting bit 0.15 (MSB of LXT970 control register) via MII I/F.

To allow external use of FCC2, its pins is appear at the CPM expansion connectors and the

50

MSC8101ADS RevB User’s Manual

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

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Page 49 Page 51
Contents MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Related Documentation IntroductionAbbreviations’ List Characteristics Specifications SpecificationMSC8101ADS Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting HReset Configuration Source Setting The Core Supply Voltage LevelSetting MODCK13 For Initial PLLs’ Multiplication Factor SW9 OnCE Connection Scheme Host I/F OperationStand Alone Operation Host System Debug Scheme B34 +5V Power Supply Connection JTAG/OnCE Connector P6Host I/F Connector P4 P6 JTAG/OnCE Port ConnectorP4 Host I/F Connector Terminal to MSC8101ADS RS-232 ConnectionFlash Memory Simm Installation 38 10/100-Base-T Ethernet Port ConnectionFlash Memory Simm Insertion Host I/F Setting SW1 Emulator Enable EE SW2Data Bus Width Setting SW5 & SW6 Abort Switch SW3Soft Reset Sreset Switch SW4 Configuration Switch SW9 Hard Reset Hreset Switch SW7Power-On Reset Switch Preset SW8 Modck Available Clock Mode SettingBoot Mode Select SW10 CPMJumpers Software Options Switch SW11431 JP1 DLL Disable 432 JP2 Clock Buffer Set437 JP9 5V power supply for Codec 433 JP3 50 Ohm Enable436 JP6,JP7 MIC Enable 434 JP4 VPP Source SelectorLEDs ATM RX Indicator LD6 Ethernet Link Indicator LD4Fast Ethernet Clsn Indicator LD5 ATM TX Indicator LD7MSC8101’s Registers’ Programming Memory Controller Registers Programming SIU Registers’ ProgrammingSystem Initialization Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Power On Reset Configuration Reset & Reset ConfigurationPower- On Reset Manual Hard ResetSummary Reset Configuration Schemes Hard Reset Configuration WordManual Soft Reset IRQ2Local Interrupter Clock GeneratorBus Buffering Chip Select GeneratorSynchronous Dram Bank MSC8101ADS Chip Select Assignments Bus Timing MachineSdram MHz Sdram Mode Register ProgrammingSdram Programming Sdram Refresh Cycle Type \ Flash Delay nsecFlash Memory Simm Flash Simm Connection Scheme Flash Programming VoltageCommunication Ports Ports Function Enable MSC8101 I/O Ports/Name581 ATM Port 582 100/10 Base T Port5831 CS4221 Programming CS4221 ProgrammingAudio Codec 585 RS232 Ports CS4221 Programming584 T1/E1 Ports Host I/F Board Control & Status Register Bcsr Host I/F Interconnect signalsDMA off-board tool BIT Mnemonic BCSR0 DescriptionBCSR0 Board Control / Status Register PON ATT DEF HostcspBCSR1 Board Control / Status Register BCSR0 Description10. BCSR1 Description Fethien 10. BCSR1 DescriptionPON ATT DEF Atmrst FethrstBCSR2 Board Control / Status Register 11. Peripheral’s Availability Decoding12. BCSR2 Description 14. Flash Presence Detect 41 Encoding 12. BCSR2 Description13. Flash Presence Detect 75 Encoding BCSR3 Board Status Register15. BCSR3 Description 18. ADS Revision Encoding 16. EXTOOLI03 Assignment17. External Tool Revision Encoding EngineeringPPC Bus Memory Map MSC8101ADS Memory Map FF000000 Ffffffff MSC8101ADS Memory MapFE000000 Ffffffff FF800000 FfffffffPower rails ADS Power Scheme712 3V Bus Off-Board Application Maximum Current Consumption711 5V Bus 713 5V BusAppendix a MSC8101 Bill of Material A1 BOM Table A-1. MSC8101ADS Bill Of MaterialFreescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information Interconnect Signals B11Table B1-2. P1 System Expansion Interconnect Signals TSTAT1 GNDTSTAT0 TSTAT2 TSTAT3 TSTAT4 TSTAT5Clkx Damage to the PM5350 ATM UNIEXPD2 EXPD0EXPD1 EXPD3EXPCTL0 SCC1RXD PD30 Table B1-3. P2 CPM Expansion Interconnect SignalsB12 MSC8101ADS’s P2 CPM Expansion Connector Hwrds SPICLKPD18SPIMOSIPD17 PD7Atmrfclk Atmtsoc PA29Atmrsoc PA27 Atmrca PA26ATMRXD5 PA15 ATMRXD7 PA17ATMRXD6 PA16 ATMRXD4 PA14Fethcol PB27 Fethtxen PB29Fethrxer PB28 Fethcrs PB26HD2 HD0HD1 HD3Atmfclk PC26 Fethmdc PC13PC6 Fethmdio PC12PC7 SMCTX1PC5B13 Table B1-4. P3 ISP Connector Interconnect SignalsB14 P4 Host Interface Connector Hack HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9HA1 HA2 HA3 HCS1 HreqB16 Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors HDSB18 P15,P16 SMB Connectors Table B1-7. P12 Ethernet Port Interconnect SignalsB17 P12 Ethernet Port Connector B19 P17,P18 Double RJ45 T1/E1 Line ConnectorsB110 P19,P21,P24 Stereo Phone Jack Connectors B111 P20,P22,P23,P25 RCA Jack ConnectorsB112 P26 5V Power Supply Connectors Table B1-10. P27A Interconnect SignalsTable B1-11. P27B Interconnect Signals B113 P27A,B RS232 Ports’ ConnectorsFreescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc Logic Equations C11 First Include FileC12 Second Include file C13 Main File Constant SIZE1 Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant EE45HOLDVALUE ConstantSRESET~ Constant TCPCDEFAULT0 Constant TCPCDEFAULT1HDIMDEN~ Host SW Enable RSTCNF~ Output HRESET~ BidirHDIEN~ SBOOTENOUT~SPARE1 Output HRRQEN~WDTIMER3 WDTIMER1WDTIMER2 WDTIMER4BCSR1 SBOOTEN~ EepromenableResets Cleartowdctrl Scndcfgbyteread Thirdcfgbyteread FourthcfgbytereadBCSR1PONDEF0..SIZE1 BCSR3IRQ0 BCSR3PONDEF0..SIZE3BCSR0 BCSR0PONCONST0..5 Begin DefaultsEND Defaults END if END Generate EEDPONDEFAULT,RSV37PONDEFAULTElse PSDVAL~ = Opndrnvcc EE PinsRegularpoweronreset = RPORI~ == Regularponresetactive END ifElse Hdiwr = If Hdds thenIf !HDSP then Hdiwr = END if ElseElsif MPCWRITEBCSR5 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR6 thenElsif MPCREADBCSR3 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenIf MPCREADBCSR0 then Elsif Firstcfgbyteread then HRESET~ =SRESET~ = Elsif Scndcfgbyteread thenElse SIGLAMP1OUT~ Then SIGLAMP0OUT~ = GND ElseThen SIGLAMP1OUT~ END if If !T1234EN~ & FETHIEN~ then116 MODCK1-3 Driven END if Drive Poreset Impulse Reconfig Using BCSR4Watchdog for Auto Reconfiguration 118
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