Nortel Networks MSC8101 ADS user manual Fethtxen PB29, Fethrxer PB28, Fethcol PB27, Fethcrs PB26

Page 87

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

TABLE B1-3. P2 - CPM Expansion - Interconnect Signals

Pin No.

Signal Name

Attribute

Description

 

 

 

 

 

 

 

 

C3

FETHTXEN (PB29)

I/O, T.S.

Fast-Ethernet Transmit Enable (H). The MSC8101 will assert

 

 

 

(High) this line, to indicate data valid on the FETHTXD(3:0) lines.

 

 

 

When the Fast-Ethernet port is disabled, this line may be used for

 

 

 

any available function of PB29.

 

 

 

 

C4

FETHRXER (PB28)

I/O, T.S.

Fast-Ethernet Receive Error (H). When this signal is asserted

 

 

 

(High) by the LXT970, while the Ethernet port is enabled and

 

 

 

FETHRXCK goes high, it indicates that the port is receiving

 

 

 

invalid data symbols from the network.

 

 

 

When the Ethernet port is disabled, this line is tristated and may

 

 

 

be used for any available function of PB28.

 

 

 

 

C5

FETHCOL (PB27)

I/O, T.S.

Fast-Ethernet Port Collision Detected (H). When this signal is

 

 

 

asserted (High) by the LXT970, while the ethernet port is enabled,

 

 

 

it indicates a Collision state over the line. When the LXT970 is in

 

 

 

Full-Duplex mode, this line is inactive.

 

 

 

When the Ethernet port is disabled, this line is tristated and may

 

 

 

be used for any available function of the PB27.

 

 

 

 

C6

FETHCRS (PB26)

I/O, T.S.

Fast-Ethernet Carrier Sense (H). When this signal is asserted

 

 

 

(High), while the Ethernet port is enabled and the LXT970 is in

 

 

 

half-duplex mode, it indicates that either the transmit or receive

 

 

 

media are non-idle. When the LXT970 is in either full-duplex or

 

 

 

repeater operation, it indicates that the receive medium is non-

 

 

 

idle.

 

 

 

When the Ethernet port is disabled, this line may be used for any

 

 

 

available function of PB26.

 

 

 

 

C7

FETHTXD3 (PB25)

I/O, T.S.

Fast Ethernet Transmit Data (3:0). This is the MII transmit data

 

 

 

bus. The MSC8101 drives these lines according to rising edge of

C8

FETHTXD2 (PB24)

 

 

FETHTXCK.

 

 

 

When the ethernet port is disabled, these lines may be used for

C9

FETHTXD1 (PB23)

 

 

any available respective function.

 

 

 

C10

FETHTXD0 (PB22)

 

 

 

 

 

 

C11

FETHRXD0 (PB21)

I/O, T.S.

Fast Ethernet Receive Data (3:0). This is the MII receive data

 

 

 

bus. The LXT970 drives these lines according to rising edge of

C12

FETHRXD1 (PB20)

 

 

FETHRXCK.

 

 

 

When the ethernet port is disabled, these lines are tristated and

C13

FETHRXD2 (PB19)

 

 

may be used for any available respective parenthesized function.

 

 

 

C14

FETHRXD3 (PB18)

 

 

 

 

 

 

B-86

MSC8101ADS RevB User’s Manual

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

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Contents MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Introduction Abbreviations’ ListRelated Documentation Specification MSC8101ADS SpecificationsCharacteristics Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting The Core Supply Voltage Level Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9Setting HReset Configuration Source Host I/F Operation OnCE Connection SchemeHost System Debug Scheme B Stand Alone OperationJTAG/OnCE Connector P6 34 +5V Power Supply ConnectionP6 JTAG/OnCE Port Connector Host I/F Connector P4Terminal to MSC8101ADS RS-232 Connection P4 Host I/F Connector38 10/100-Base-T Ethernet Port Connection Flash Memory Simm InstallationFlash Memory Simm Insertion Emulator Enable EE SW2 Host I/F Setting SW1Abort Switch SW3 Soft Reset Sreset Switch SW4Data Bus Width Setting SW5 & SW6 Hard Reset Hreset Switch SW7 Power-On Reset Switch Preset SW8Configuration Switch SW9 CPM Available Clock Mode SettingBoot Mode Select SW10 Modck432 JP2 Clock Buffer Set Software Options Switch SW11431 JP1 DLL Disable Jumpers434 JP4 VPP Source Selector 433 JP3 50 Ohm Enable436 JP6,JP7 MIC Enable 437 JP9 5V power supply for CodecLEDs ATM TX Indicator LD7 Ethernet Link Indicator LD4Fast Ethernet Clsn Indicator LD5 ATM RX Indicator LD6MSC8101’s Registers’ Programming SIU Registers’ Programming System InitializationMemory Controller Registers Programming Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Manual Hard Reset Reset & Reset ConfigurationPower- On Reset Power On Reset ConfigurationHard Reset Configuration Word Summary Reset Configuration SchemesIRQ2 Manual Soft ResetClock Generator Local InterrupterChip Select Generator Bus BufferingMSC8101ADS Chip Select Assignments Bus Timing Machine Synchronous Dram BankMHz Sdram Mode Register Programming Sdram ProgrammingSdram Cycle Type \ Flash Delay nsec Flash Memory SimmSdram Refresh Flash Programming Voltage Flash Simm Connection SchemeCommunication Ports MSC8101 I/O Ports/Name Ports Function Enable582 100/10 Base T Port 581 ATM PortCS4221 Programming Audio Codec5831 CS4221 Programming CS4221 Programming 584 T1/E1 Ports585 RS232 Ports Host I/F Host I/F Interconnect signals DMA off-board toolBoard Control & Status Register Bcsr PON ATT DEF Hostcsp BCSR0 DescriptionBCSR0 Board Control / Status Register BIT MnemonicBCSR0 Description 10. BCSR1 DescriptionBCSR1 Board Control / Status Register Fethrst 10. BCSR1 DescriptionPON ATT DEF Atmrst Fethien11. Peripheral’s Availability Decoding 12. BCSR2 DescriptionBCSR2 Board Control / Status Register BCSR3 Board Status Register 12. BCSR2 Description13. Flash Presence Detect 75 Encoding 14. Flash Presence Detect 41 Encoding15. BCSR3 Description Engineering 16. EXTOOLI03 Assignment17. External Tool Revision Encoding 18. ADS Revision EncodingPPC Bus Memory Map MSC8101ADS Memory Map FF800000 Ffffffff MSC8101ADS Memory MapFE000000 Ffffffff FF000000 FfffffffADS Power Scheme Power rails713 5V Bus Off-Board Application Maximum Current Consumption711 5V Bus 712 3V BusAppendix a MSC8101 Bill of Material Table A-1. MSC8101ADS Bill Of Material A1 BOMFreescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information B11 Interconnect SignalsTable B1-2. P1 System Expansion Interconnect Signals TSTAT2 TSTAT3 TSTAT4 TSTAT5 GNDTSTAT0 TSTAT1Damage to the PM5350 ATM UNI ClkxEXPD3 EXPD0EXPD1 EXPD2EXPCTL0 Table B1-3. P2 CPM Expansion Interconnect Signals B12 MSC8101ADS’s P2 CPM Expansion ConnectorSCC1RXD PD30 PD7 SPICLKPD18 SPIMOSIPD17 HwrdsAtmrca PA26 Atmtsoc PA29Atmrsoc PA27 AtmrfclkATMRXD4 PA14 ATMRXD7 PA17ATMRXD6 PA16 ATMRXD5 PA15Fethcrs PB26 Fethtxen PB29Fethrxer PB28 Fethcol PB27HD3 HD0HD1 HD2Fethmdc PC13 Atmfclk PC26SMCTX1PC5 Fethmdio PC12PC7 PC6Table B1-4. P3 ISP Connector Interconnect Signals B14 P4 Host Interface ConnectorB13 Hreq HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9HA1 HA2 HA3 HCS1 HackHDS Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors B16B19 P17,P18 Double RJ45 T1/E1 Line Connectors Table B1-7. P12 Ethernet Port Interconnect SignalsB17 P12 Ethernet Port Connector B18 P15,P16 SMB ConnectorsB111 P20,P22,P23,P25 RCA Jack Connectors B110 P19,P21,P24 Stereo Phone Jack ConnectorsB113 P27A,B RS232 Ports’ Connectors Table B1-10. P27A Interconnect SignalsTable B1-11. P27B Interconnect Signals B112 P26 5V Power Supply ConnectorsFreescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc C11 First Include File Logic EquationsC12 Second Include file C13 Main File Constant Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant EE45HOLDVALUE Constant SIZE1HRESET~ Bidir Constant TCPCDEFAULT0 Constant TCPCDEFAULT1HDIMDEN~ Host SW Enable RSTCNF~ Output SRESET~HRRQEN~ SBOOTENOUT~SPARE1 Output HDIEN~WDTIMER4 WDTIMER1WDTIMER2 WDTIMER3Scndcfgbyteread Thirdcfgbyteread Fourthcfgbyteread EepromenableResets Cleartowdctrl BCSR1 SBOOTEN~BCSR3PONDEF0..SIZE3 BCSR3IRQ0 BCSR1PONDEF0..SIZE1Begin Defaults END DefaultsBCSR0 BCSR0PONCONST0..5 EEDPONDEFAULT,RSV37PONDEFAULT ElseEND if END Generate END if EE PinsRegularpoweronreset = RPORI~ == Regularponresetactive PSDVAL~ = OpndrnvccEND if Else If Hdds thenIf !HDSP then Hdiwr = Else Hdiwr =Elsif MPCWRITEBCSR6 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR5 thenSIGNALLAMP1~ Elsif MPCREADBCSR1 then If MPCREADBCSR0 thenElsif MPCREADBCSR3 then Elsif Scndcfgbyteread then HRESET~ =SRESET~ = Elsif Firstcfgbyteread thenEND if If !T1234EN~ & FETHIEN~ then Then SIGLAMP0OUT~ = GND ElseThen SIGLAMP1OUT~ Else SIGLAMP1OUT~116 END if Drive Poreset Impulse Reconfig Using BCSR4 Watchdog for Auto ReconfigurationMODCK1-3 Driven 118
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