Nortel Networks MSC8101 ADS Atmtsoc PA29, Atmrsoc PA27, Atmrfclk, Atmrca PA26, ATMTXD0 PA25

Page 85

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

TABLE B1-3. P2 - CPM Expansion - Interconnect Signals

Pin No.

Signal Name

Attribute

Description

 

 

 

 

 

 

 

 

B2

ATMTCAb (PA30)

I/O, T.S.

ATM Transmit Cell Available (H). When this signal is asserted

 

 

 

(High), while the ATM port is enabled, it indicates that the transmit

 

 

 

FIFO of the PM5350 is empty and ready to except a new cell.

 

 

 

When negated, it may show either that the transmit FIFO is Full or

 

 

 

close to Full, depending on PM5350 internal programming.

 

 

 

When the ATM port is disabled, this line may be used for any

 

 

 

available function of PA30.

 

 

 

 

B3

ATMTSOC (PA29)

I/O, T.S.

ATM Transmit Start Of Cell (H). When this signal is asserted

 

 

 

(High) by the MSC8101, while the ATM port is enabled, it

 

 

 

indicates to the PM5350 the start of a new ATM cell over

 

 

 

ATMTXD(7:0), i.e., the 1’st octet is present there.

 

 

 

When the ATM port is disabled, this line may be used for any

 

 

 

available function of PA29.

 

 

 

 

B4

ATMRXENb (PA28)

I/O, T.S.

ATM Receive Enable (L). When this signal is asserted (Low),

 

 

 

while the ATM port is enabled and ATMRFCLKb goes high, on

 

 

 

octet of data is available at the PM5350’s ATMRXD(7:0) lines.

 

 

 

When negated while ATMRFCLK goes high data on

 

 

 

ATMRXD(7:0) is invalid, however driven.

 

 

 

When the ATM port is disabled, this line may be used for any

 

 

 

available function for PA28.

 

 

 

 

B5

ATMRSOC (PA27)

I/O, T.S.

ATM Receive Start Of Cell (H). When this signal is asserted

 

 

 

(High), while the ATM port is enabled, it indicates, that the 1’st

 

 

 

octet of data for the received cell is available at the PM5350’s

 

 

 

ATMRXD(7:0) lines. This line is updated over the rising edge of

 

 

 

ATMRFCLK.

 

 

 

When the ATM port is disabled, this line is tristated and may be

 

 

 

used for any available function for PA27.

 

 

 

 

B6

ATMRCA (PA26)

I/O, T.S.

ATM Receive Cell Available (H). When this signal is asserted

 

 

 

(High), while the ATM port is enabled and ATMRFCLK goes high,

 

 

 

it indicates that the PM5350’s receive FIFO is either full or that

 

 

 

there are 4 empty bytes left in it - PM5350 internal programming

 

 

 

dependent.

 

 

 

When the ATM port is disabled, this line is tristated and may be

 

 

 

used for any available function of PA26.

 

 

 

 

B7

ATMTXD0 (PA25)

I/O, T.S.

ATM Transmit Data (7c:0). When the ATM port is enabled, this

 

 

 

bus carries the ATM cell octets, written to the PM5350’s transmit

B8

ATMTXD1 (PA24)

 

 

FIFO. This bus is considered valid only when ATMTXENb is

 

 

 

asserted and are sampled on the rising edge of ATMTFCLK.

B9

ATMTXD2 (PA23)

 

 

When the ATM port is disabled, these lines may be used for any

 

 

 

B10

ATMTXD3 (PA22)

 

available respective function.

 

 

 

 

B11

ATMTXD4 (PA21)

 

 

 

 

 

 

B12

ATMTXD5 (PA20)

 

 

 

 

 

 

B13

ATMTXD6 (PA19)

 

 

 

 

 

 

B14

ATMTXD7 (PA18)

 

 

 

 

 

 

B-84

MSC8101ADS RevB User’s Manual

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Page 84 Page 86
Image 85
Page 84 Page 86
Contents MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Abbreviations’ List IntroductionRelated Documentation MSC8101ADS Specifications SpecificationCharacteristics Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9 Setting The Core Supply Voltage LevelSetting HReset Configuration Source Host I/F Operation OnCE Connection SchemeHost System Debug Scheme B Stand Alone OperationJTAG/OnCE Connector P6 34 +5V Power Supply ConnectionP6 JTAG/OnCE Port Connector Host I/F Connector P4Terminal to MSC8101ADS RS-232 Connection P4 Host I/F Connector38 10/100-Base-T Ethernet Port Connection Flash Memory Simm InstallationFlash Memory Simm Insertion Emulator Enable EE SW2 Host I/F Setting SW1Soft Reset Sreset Switch SW4 Abort Switch SW3Data Bus Width Setting SW5 & SW6 Power-On Reset Switch Preset SW8 Hard Reset Hreset Switch SW7Configuration Switch SW9 Boot Mode Select SW10 Available Clock Mode SettingModck CPM431 JP1 DLL Disable Software Options Switch SW11Jumpers 432 JP2 Clock Buffer Set436 JP6,JP7 MIC Enable 433 JP3 50 Ohm Enable437 JP9 5V power supply for Codec 434 JP4 VPP Source SelectorLEDs Fast Ethernet Clsn Indicator LD5 Ethernet Link Indicator LD4ATM RX Indicator LD6 ATM TX Indicator LD7MSC8101’s Registers’ Programming System Initialization SIU Registers’ ProgrammingMemory Controller Registers Programming Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Power- On Reset Reset & Reset ConfigurationPower On Reset Configuration Manual Hard ResetHard Reset Configuration Word Summary Reset Configuration SchemesIRQ2 Manual Soft ResetClock Generator Local InterrupterChip Select Generator Bus BufferingMSC8101ADS Chip Select Assignments Bus Timing Machine Synchronous Dram BankSdram Programming MHz Sdram Mode Register ProgrammingSdram Flash Memory Simm Cycle Type \ Flash Delay nsecSdram Refresh Flash Programming Voltage Flash Simm Connection SchemeCommunication Ports MSC8101 I/O Ports/Name Ports Function Enable582 100/10 Base T Port 581 ATM PortAudio Codec CS4221 Programming5831 CS4221 Programming 584 T1/E1 Ports CS4221 Programming585 RS232 Ports Host I/F DMA off-board tool Host I/F Interconnect signalsBoard Control & Status Register Bcsr BCSR0 Board Control / Status Register BCSR0 DescriptionBIT Mnemonic PON ATT DEF Hostcsp10. BCSR1 Description BCSR0 DescriptionBCSR1 Board Control / Status Register PON ATT DEF Atmrst 10. BCSR1 DescriptionFethien Fethrst12. BCSR2 Description 11. Peripheral’s Availability DecodingBCSR2 Board Control / Status Register 13. Flash Presence Detect 75 Encoding 12. BCSR2 Description14. Flash Presence Detect 41 Encoding BCSR3 Board Status Register15. BCSR3 Description 17. External Tool Revision Encoding 16. EXTOOLI03 Assignment18. ADS Revision Encoding EngineeringPPC Bus Memory Map MSC8101ADS Memory Map FE000000 Ffffffff MSC8101ADS Memory MapFF000000 Ffffffff FF800000 FfffffffADS Power Scheme Power rails711 5V Bus Off-Board Application Maximum Current Consumption712 3V Bus 713 5V BusAppendix a MSC8101 Bill of Material Table A-1. MSC8101ADS Bill Of Material A1 BOMFreescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information B11 Interconnect SignalsTable B1-2. P1 System Expansion Interconnect Signals TSTAT0 GNDTSTAT1 TSTAT2 TSTAT3 TSTAT4 TSTAT5Damage to the PM5350 ATM UNI ClkxEXPD1 EXPD0EXPD2 EXPD3 EXPCTL0 B12 MSC8101ADS’s P2 CPM Expansion Connector Table B1-3. P2 CPM Expansion Interconnect SignalsSCC1RXD PD30 SPIMOSIPD17 SPICLKPD18Hwrds PD7Atmrsoc PA27 Atmtsoc PA29Atmrfclk Atmrca PA26ATMRXD6 PA16 ATMRXD7 PA17ATMRXD5 PA15 ATMRXD4 PA14Fethrxer PB28 Fethtxen PB29Fethcol PB27 Fethcrs PB26HD1 HD0HD2 HD3Fethmdc PC13 Atmfclk PC26PC7 Fethmdio PC12PC6 SMCTX1PC5B14 P4 Host Interface Connector Table B1-4. P3 ISP Connector Interconnect SignalsB13 HA1 HA2 HA3 HCS1 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9Hack HreqB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB16 HDSB17 P12 Ethernet Port Connector Table B1-7. P12 Ethernet Port Interconnect SignalsB18 P15,P16 SMB Connectors B19 P17,P18 Double RJ45 T1/E1 Line ConnectorsB111 P20,P22,P23,P25 RCA Jack Connectors B110 P19,P21,P24 Stereo Phone Jack ConnectorsTable B1-11. P27B Interconnect Signals Table B1-10. P27A Interconnect SignalsB112 P26 5V Power Supply Connectors B113 P27A,B RS232 Ports’ ConnectorsFreescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc C11 First Include File Logic EquationsC12 Second Include file C13 Main File Constant EE45HOLDVALUE Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant SIZE1 ConstantHDIMDEN~ Host SW Enable RSTCNF~ Output Constant TCPCDEFAULT0 Constant TCPCDEFAULT1SRESET~ HRESET~ BidirSPARE1 Output SBOOTENOUT~HDIEN~ HRRQEN~WDTIMER2 WDTIMER1WDTIMER3 WDTIMER4Resets Cleartowdctrl EepromenableBCSR1 SBOOTEN~ Scndcfgbyteread Thirdcfgbyteread FourthcfgbytereadIRQ0 BCSR3BCSR1PONDEF0..SIZE1 BCSR3PONDEF0..SIZE3END Defaults Begin DefaultsBCSR0 BCSR0PONCONST0..5 Else EEDPONDEFAULT,RSV37PONDEFAULTEND if END Generate Regularpoweronreset = RPORI~ == Regularponresetactive EE PinsPSDVAL~ = Opndrnvcc END ifIf !HDSP then Hdiwr = If Hdds thenElse Hdiwr = END if ElseElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR5 then Elsif MPCWRITEBCSR6 thenIf MPCREADBCSR0 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenElsif MPCREADBCSR3 then SRESET~ = HRESET~ =Elsif Firstcfgbyteread then Elsif Scndcfgbyteread thenThen SIGLAMP1OUT~ Then SIGLAMP0OUT~ = GND ElseElse SIGLAMP1OUT~ END if If !T1234EN~ & FETHIEN~ then116 Watchdog for Auto Reconfiguration END if Drive Poreset Impulse Reconfig Using BCSR4MODCK1-3 Driven 118
Top Page Image Contents