Nortel Networks MSC8101 ADS user manual Host I/F

Page 53

Freescale Semiconductor, Inc.

Functional Description

to detect if a terminal is connected to the MSC8101ADS board.

•DSRA ( O ) - Data Set Ready. This line is always asserted by the MSC8101ADS.

•RTS ( I ) - Request To Send. This line is not connected in the MSC8101ADS.

•CTS ( O ) - Clear To Send. This line is always asserted by the MSC8101ADS.

5•9

Host I/F

Host processor may be connected through 16bit-wideBbidirectional parallel port multiplexed with 32 LSBC of MSC8101 Data bus. The Host I/F will be driven after hard-reset sequence if HPE pin is sampled high at the rising edge of PORESET. Since MSC8101 Data bus has 64bit width in 60x mode to provide Host I/F disconnect additional buffers will be needed. These buffers are enabled by BCSR control line. Host Dual Data Strobe (DDS), Data Strobe Polarity (DSP), Chip Select Polarity (CSP) lines and HRRQ/HACK direction are controlled by corresponding bits of the BCSR0/1-2. See FIGURE 5-6 "Host Interface Diagram" below.

Buffer/transceivers are 5V compliant.

Host Port is also available via two row header 36 pins.

Freescale Semiconductor, Inc.

FIGURE 5-6 Host Interface Diagram

D[0:63]			16bit
D[0:63]					U45
					U45
	D[32:47]
	HD[0:15]		E	DIR	from BCSR
		O.D.	E	DIR
	D[56]	O.D.			U3
	D[56]				U3
	HACK/HRRQ		E	DIR	from BCSR control bit set once
	D[55]	O.D.		U4
bus	D[55]			U4
bus	HREQ/HTRQ		E
PPC	D[48:51]			U45
	HA[0:3]
	D[52:54]
	HCS,HRW,HWR		E
	D[57:60]				O.D.
	D[57:60]			PORESET
				PORESET
	DSP, DDS,				O.D. To P2 & P4 conn.
	8BIT				O.D. To P2 & P4 conn.
	8BIT			HRESET
	Host Enable
	DIP SW

BCSR controlled

To P2-CPM & P4-HOST conn

Presence Detect Pin (PDP)

The MSC8101 CPM ports are poorer than the MPC8260 CPM, therefore Host I/F bus may be driven outside through CPM Expansion Connector in place of unusable lines. Since the CPM Ex-

A. Since there are only 3 RS232 transmitters in the device, DSR is connected to CD.

B. 8-bit mode is also available for HDI8 I/F.

C. Really 28pins are used for Host interface.

MOTOROLA

MSC8101ADS RevB User’s Manual

53

For More Information On This Product,

Go to: www.freescale.com

Image 53

Contents MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Related Documentation IntroductionAbbreviations’ List Characteristics Specifications SpecificationMSC8101ADS Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting HReset Configuration Source Setting The Core Supply Voltage LevelSetting MODCK13 For Initial PLLs’ Multiplication Factor SW9 Host I/F Operation OnCE Connection SchemeHost System Debug Scheme B Stand Alone OperationJTAG/OnCE Connector P6 34 +5V Power Supply ConnectionP6 JTAG/OnCE Port Connector Host I/F Connector P4Terminal to MSC8101ADS RS-232 Connection P4 Host I/F Connector38 10/100-Base-T Ethernet Port Connection Flash Memory Simm InstallationFlash Memory Simm Insertion Emulator Enable EE SW2 Host I/F Setting SW1Data Bus Width Setting SW5 & SW6 Abort Switch SW3Soft Reset Sreset Switch SW4 Configuration Switch SW9 Hard Reset Hreset Switch SW7Power-On Reset Switch Preset SW8 Boot Mode Select SW10 Available Clock Mode SettingModck CPM431 JP1 DLL Disable Software Options Switch SW11Jumpers 432 JP2 Clock Buffer Set436 JP6,JP7 MIC Enable 433 JP3 50 Ohm Enable437 JP9 5V power supply for Codec 434 JP4 VPP Source SelectorLEDs Fast Ethernet Clsn Indicator LD5 Ethernet Link Indicator LD4ATM RX Indicator LD6 ATM TX Indicator LD7MSC8101’s Registers’ Programming Memory Controller Registers Programming SIU Registers’ ProgrammingSystem Initialization Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Power- On Reset Reset & Reset ConfigurationPower On Reset Configuration Manual Hard ResetHard Reset Configuration Word Summary Reset Configuration SchemesIRQ2 Manual Soft ResetClock Generator Local InterrupterChip Select Generator Bus BufferingMSC8101ADS Chip Select Assignments Bus Timing Machine Synchronous Dram BankSdram MHz Sdram Mode Register ProgrammingSdram Programming Sdram Refresh Cycle Type \ Flash Delay nsecFlash Memory Simm Flash Programming Voltage Flash Simm Connection SchemeCommunication Ports MSC8101 I/O Ports/Name Ports Function Enable582 100/10 Base T Port 581 ATM Port5831 CS4221 Programming CS4221 ProgrammingAudio Codec 585 RS232 Ports CS4221 Programming584 T1/E1 Ports Host I/F Board Control & Status Register Bcsr Host I/F Interconnect signalsDMA off-board tool BCSR0 Board Control / Status Register BCSR0 DescriptionBIT Mnemonic PON ATT DEF HostcspBCSR1 Board Control / Status Register BCSR0 Description10. BCSR1 Description PON ATT DEF Atmrst 10. BCSR1 DescriptionFethien FethrstBCSR2 Board Control / Status Register 11. Peripheral’s Availability Decoding12. BCSR2 Description 13. Flash Presence Detect 75 Encoding 12. BCSR2 Description14. Flash Presence Detect 41 Encoding BCSR3 Board Status Register15. BCSR3 Description 17. External Tool Revision Encoding 16. EXTOOLI03 Assignment18. ADS Revision Encoding EngineeringPPC Bus Memory Map MSC8101ADS Memory Map FE000000 Ffffffff MSC8101ADS Memory MapFF000000 Ffffffff FF800000 FfffffffADS Power Scheme Power rails711 5V Bus Off-Board Application Maximum Current Consumption712 3V Bus 713 5V BusAppendix a MSC8101 Bill of Material Table A-1. MSC8101ADS Bill Of Material A1 BOMFreescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information B11 Interconnect SignalsTable B1-2. P1 System Expansion Interconnect Signals TSTAT0 GNDTSTAT1 TSTAT2 TSTAT3 TSTAT4 TSTAT5Damage to the PM5350 ATM UNI ClkxEXPD1 EXPD0EXPD2 EXPD3EXPCTL0 SCC1RXD PD30 Table B1-3. P2 CPM Expansion Interconnect SignalsB12 MSC8101ADS’s P2 CPM Expansion Connector SPIMOSIPD17 SPICLKPD18Hwrds PD7Atmrsoc PA27 Atmtsoc PA29Atmrfclk Atmrca PA26ATMRXD6 PA16 ATMRXD7 PA17ATMRXD5 PA15 ATMRXD4 PA14Fethrxer PB28 Fethtxen PB29Fethcol PB27 Fethcrs PB26HD1 HD0HD2 HD3Fethmdc PC13 Atmfclk PC26PC7 Fethmdio PC12PC6 SMCTX1PC5B13 Table B1-4. P3 ISP Connector Interconnect SignalsB14 P4 Host Interface Connector HA1 HA2 HA3 HCS1 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9Hack HreqB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB16 HDSB17 P12 Ethernet Port Connector Table B1-7. P12 Ethernet Port Interconnect SignalsB18 P15,P16 SMB Connectors B19 P17,P18 Double RJ45 T1/E1 Line ConnectorsB111 P20,P22,P23,P25 RCA Jack Connectors B110 P19,P21,P24 Stereo Phone Jack ConnectorsTable B1-11. P27B Interconnect Signals Table B1-10. P27A Interconnect SignalsB112 P26 5V Power Supply Connectors B113 P27A,B RS232 Ports’ ConnectorsFreescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc C11 First Include File Logic EquationsC12 Second Include file C13 Main File Constant EE45HOLDVALUE Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant SIZE1 ConstantHDIMDEN~ Host SW Enable RSTCNF~ Output Constant TCPCDEFAULT0 Constant TCPCDEFAULT1SRESET~ HRESET~ BidirSPARE1 Output SBOOTENOUT~HDIEN~ HRRQEN~WDTIMER2 WDTIMER1WDTIMER3 WDTIMER4Resets Cleartowdctrl EepromenableBCSR1 SBOOTEN~ Scndcfgbyteread Thirdcfgbyteread FourthcfgbytereadIRQ0 BCSR3BCSR1PONDEF0..SIZE1 BCSR3PONDEF0..SIZE3BCSR0 BCSR0PONCONST0..5 Begin DefaultsEND Defaults END if END Generate EEDPONDEFAULT,RSV37PONDEFAULTElse Regularpoweronreset = RPORI~ == Regularponresetactive EE PinsPSDVAL~ = Opndrnvcc END ifIf !HDSP then Hdiwr = If Hdds thenElse Hdiwr = END if ElseElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR5 then Elsif MPCWRITEBCSR6 thenElsif MPCREADBCSR3 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenIf MPCREADBCSR0 then SRESET~ = HRESET~ =Elsif Firstcfgbyteread then Elsif Scndcfgbyteread thenThen SIGLAMP1OUT~ Then SIGLAMP0OUT~ = GND ElseElse SIGLAMP1OUT~ END if If !T1234EN~ & FETHIEN~ then116 MODCK1-3 Driven END if Drive Poreset Impulse Reconfig Using BCSR4Watchdog for Auto Reconfiguration 118