Nortel Networks MSC8101 ADS user manual HD0, HD1, HD2, HD3, HD4, HD5, HD6, HD7, HD8, HD9, Atmrclk

Page 88

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

TABLE B1-3. P2 - CPM Expansion - Interconnect Signals

 

Pin No.

Signal Name

Attribute

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C15

HD0

I/O, T.S.

Host Interface Bidirectional Data Port D0-D13. Present as well as

 

 

 

 

 

at P4 connector.

 

 

C16

HD1

 

 

 

 

 

 

 

 

 

 

 

 

 

C17

HD2

 

 

 

 

 

 

 

 

 

 

C18

HD3

 

 

 

 

 

 

 

 

 

 

C19

HD4

 

 

 

 

 

 

 

 

 

 

C20

HD5

 

 

 

 

 

 

 

 

 

 

C21

HD6

 

 

 

 

 

 

 

 

 

 

C22

HD7

 

 

 

 

 

 

 

 

 

 

C23

HD8

 

 

 

 

 

 

 

 

 

 

C24

HD9

 

 

 

 

 

 

 

 

 

 

C25

HD10

 

 

 

 

 

 

 

 

 

 

C26

HD11

 

 

 

 

 

 

 

 

 

 

C27

HD12

 

 

 

 

 

 

 

 

 

 

C28

HD13

 

 

 

 

 

 

 

 

 

 

C29

ATMRCLK

O, T.S.

ATM Receive Clock. A divide by 8 of the ATM line clock recovered

 

 

 

 

 

by the ATM receive logic. Enabled only when pin A29 of this

 

 

 

 

 

connector is either not connected or driven low. Otherwise, Tri-

 

 

 

 

 

stated.

 

 

 

 

 

 

 

 

C30

GND

P

Digital Ground. Connected to main GND plane of the ADS.

 

 

 

 

 

 

 

 

C31

 

 

 

 

 

 

 

 

 

 

 

C32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D1

CLK1(PC31)

I/O, T.S.

Clock 1 input. When TDMA is enabled this pin is an input clock.

 

 

 

 

 

When TDMA port is disabled this line may be used for any

 

 

 

 

 

available function of PC31 Port C.

 

 

 

 

 

 

 

 

D2

PC30

I/O, T.S.

MSC8101’s Port C30 Parallel I/O line. May be used to any of its

 

 

 

 

 

available functions.

 

 

 

 

 

 

 

 

D3

FETHRXCK (PC29)

I/O, T.S.

Fast-Ethernet Receive Clock. When the Ethernet port is enabled,

 

 

 

 

 

this clock (25 MHz for 100 Mbps, 2.5 MHz for 10 Mbps) is

 

 

 

 

 

extracted from the received data and driven to the MSC8101 to

 

 

 

 

 

qualify incoming receive data.

 

 

 

 

 

When the Ethernet port is disabled, this line is tristated and may

 

 

 

 

 

be used for any available function of PC29.

 

 

 

 

 

 

 

 

D4

FETHTXCK (PC28)

I/O, T.S.

Fast-Ethernet Transmit Clock. When the Ethernet port is enabled,

 

 

 

 

 

this clock (25 MHz for 100 Mbps, 2.5 MHz for 10 Mbps) is

 

 

 

 

 

normally extracted from the received data and driven to the

 

 

 

 

 

MSC8101 to qualify out coming transmit data. In Slave mode (not

 

 

 

 

 

used with this application) this clock should be input to the

 

 

 

 

 

LXT970.

 

 

 

 

 

When the Ethernet port is disabled, this line is tristated and may

 

 

 

 

 

be used for any available function of PC28.

 

 

 

 

 

 

 

 

 

 

 

 

 

MOTOROLA

MSC8101ADS RevB User’s Manual

B-87

For More Information On This Product,

Go to: www.freescale.com

Page 87 Page 89
Image 88
Page 87 Page 89
Contents MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Abbreviations’ List IntroductionRelated Documentation MSC8101ADS Specifications SpecificationCharacteristics Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9 Setting The Core Supply Voltage LevelSetting HReset Configuration Source OnCE Connection Scheme Host I/F OperationStand Alone Operation Host System Debug Scheme B34 +5V Power Supply Connection JTAG/OnCE Connector P6Host I/F Connector P4 P6 JTAG/OnCE Port ConnectorP4 Host I/F Connector Terminal to MSC8101ADS RS-232 ConnectionFlash Memory Simm Installation 38 10/100-Base-T Ethernet Port ConnectionFlash Memory Simm Insertion Host I/F Setting SW1 Emulator Enable EE SW2Soft Reset Sreset Switch SW4 Abort Switch SW3Data Bus Width Setting SW5 & SW6 Power-On Reset Switch Preset SW8 Hard Reset Hreset Switch SW7Configuration Switch SW9 Available Clock Mode Setting Boot Mode Select SW10Modck CPMSoftware Options Switch SW11 431 JP1 DLL DisableJumpers 432 JP2 Clock Buffer Set433 JP3 50 Ohm Enable 436 JP6,JP7 MIC Enable437 JP9 5V power supply for Codec 434 JP4 VPP Source SelectorLEDs Ethernet Link Indicator LD4 Fast Ethernet Clsn Indicator LD5ATM RX Indicator LD6 ATM TX Indicator LD7MSC8101’s Registers’ Programming System Initialization SIU Registers’ ProgrammingMemory Controller Registers Programming Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Reset & Reset Configuration Power- On ResetPower On Reset Configuration Manual Hard ResetSummary Reset Configuration Schemes Hard Reset Configuration WordManual Soft Reset IRQ2Local Interrupter Clock GeneratorBus Buffering Chip Select GeneratorSynchronous Dram Bank MSC8101ADS Chip Select Assignments Bus Timing MachineSdram Programming MHz Sdram Mode Register ProgrammingSdram Flash Memory Simm Cycle Type \ Flash Delay nsecSdram Refresh Flash Simm Connection Scheme Flash Programming VoltageCommunication Ports Ports Function Enable MSC8101 I/O Ports/Name581 ATM Port 582 100/10 Base T PortAudio Codec CS4221 Programming5831 CS4221 Programming 584 T1/E1 Ports CS4221 Programming585 RS232 Ports Host I/F DMA off-board tool Host I/F Interconnect signalsBoard Control & Status Register Bcsr BCSR0 Description BCSR0 Board Control / Status RegisterBIT Mnemonic PON ATT DEF Hostcsp10. BCSR1 Description BCSR0 DescriptionBCSR1 Board Control / Status Register 10. BCSR1 Description PON ATT DEF AtmrstFethien Fethrst12. BCSR2 Description 11. Peripheral’s Availability DecodingBCSR2 Board Control / Status Register 12. BCSR2 Description 13. Flash Presence Detect 75 Encoding14. Flash Presence Detect 41 Encoding BCSR3 Board Status Register15. BCSR3 Description 16. EXTOOLI03 Assignment 17. External Tool Revision Encoding18. ADS Revision Encoding EngineeringPPC Bus Memory Map MSC8101ADS Memory Map MSC8101ADS Memory Map FE000000 FfffffffFF000000 Ffffffff FF800000 FfffffffPower rails ADS Power SchemeOff-Board Application Maximum Current Consumption 711 5V Bus712 3V Bus 713 5V BusAppendix a MSC8101 Bill of Material A1 BOM Table A-1. MSC8101ADS Bill Of MaterialFreescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information Interconnect Signals B11Table B1-2. P1 System Expansion Interconnect Signals GND TSTAT0TSTAT1 TSTAT2 TSTAT3 TSTAT4 TSTAT5Clkx Damage to the PM5350 ATM UNIEXPD0 EXPD1EXPD2 EXPD3EXPCTL0 B12 MSC8101ADS’s P2 CPM Expansion Connector Table B1-3. P2 CPM Expansion Interconnect SignalsSCC1RXD PD30 SPICLKPD18 SPIMOSIPD17Hwrds PD7 Atmtsoc PA29 Atmrsoc PA27 Atmrfclk Atmrca PA26ATMRXD7 PA17 ATMRXD6 PA16ATMRXD5 PA15 ATMRXD4 PA14Fethtxen PB29 Fethrxer PB28Fethcol PB27 Fethcrs PB26HD0 HD1HD2 HD3Atmfclk PC26 Fethmdc PC13Fethmdio PC12 PC7PC6 SMCTX1PC5B14 P4 Host Interface Connector Table B1-4. P3 ISP Connector Interconnect SignalsB13 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HA1 HA2 HA3 HCS1Hack HreqTable B1-6. P6 JTAG/ONCE Connector Interconnect Signals B15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer ConnectorsB16 HDSTable B1-7. P12 Ethernet Port Interconnect Signals B17 P12 Ethernet Port ConnectorB18 P15,P16 SMB Connectors B19 P17,P18 Double RJ45 T1/E1 Line ConnectorsB110 P19,P21,P24 Stereo Phone Jack Connectors B111 P20,P22,P23,P25 RCA Jack ConnectorsTable B1-10. P27A Interconnect Signals Table B1-11. P27B Interconnect SignalsB112 P26 5V Power Supply Connectors B113 P27A,B RS232 Ports’ ConnectorsFreescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc Logic Equations C11 First Include FileC12 Second Include file C13 Main File Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0 Constant EE45HOLDVALUEConstant SIZE1 ConstantConstant TCPCDEFAULT0 Constant TCPCDEFAULT1 HDIMDEN~ Host SW Enable RSTCNF~ OutputSRESET~ HRESET~ BidirSBOOTENOUT~ SPARE1 OutputHDIEN~ HRRQEN~WDTIMER1 WDTIMER2WDTIMER3 WDTIMER4Eepromenable Resets CleartowdctrlBCSR1 SBOOTEN~ Scndcfgbyteread Thirdcfgbyteread FourthcfgbytereadBCSR3 IRQ0BCSR1PONDEF0..SIZE1 BCSR3PONDEF0..SIZE3END Defaults Begin DefaultsBCSR0 BCSR0PONCONST0..5 Else EEDPONDEFAULT,RSV37PONDEFAULTEND if END Generate EE Pins Regularpoweronreset = RPORI~ == RegularponresetactivePSDVAL~ = Opndrnvcc END ifIf Hdds then If !HDSP then Hdiwr =Else Hdiwr = END if ElseElsif MPCWRITEBCSR1 then Elsif MPCWRITEBCSR4 thenElsif MPCWRITEBCSR5 then Elsif MPCWRITEBCSR6 thenIf MPCREADBCSR0 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenElsif MPCREADBCSR3 then HRESET~ = SRESET~ =Elsif Firstcfgbyteread then Elsif Scndcfgbyteread thenThen SIGLAMP0OUT~ = GND Else Then SIGLAMP1OUT~Else SIGLAMP1OUT~ END if If !T1234EN~ & FETHIEN~ then116 Watchdog for Auto Reconfiguration END if Drive Poreset Impulse Reconfig Using BCSR4MODCK1-3 Driven 118
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