Nortel Networks MSC8101 ADS user manual Bus Buffering, Chip Select Generator

Page 43

CLOCK OSC.

55MHz/

20MHz

Freescale Semiconductor, Inc.

Functional Description

FIGURE 5-1 Clock Distribution Scheme

 

 

 

CY2309

A1

SDRAM1

 

 

 

Zero

MSC8101

 

 

 

A2

 

 

Delay

SDRAM2

 

 

 

Buffer

 

 

CLKIN

CLKOUT

 

 

B1

BCSR

 

 

VCC

 

DLL_IN

 

B2

MICTOR

 

 

 

JP2

VCC/

S2

B3

EXPANSION

 

 

S1

A4

 

 

 

GND

 

 

 

 

 

U44

 

 

Freescale Semiconductor, Inc.

The Zero Delay Buffer CY2309 distributes high speed clock with skew less 250ps when internal PLL is ON. Select inputs S1,S2 allow to the input clock be directly applied to the output with pro- pogation delay of regular clock buffer about 5ns. See available working modes in TABLE 4-2. "JP1/ JP2 Settings".

5•4 Bus Buffering

In order to achieve best performance, it is necessary to reduce the capacitive load over the PPC bus as much as possible. Therefore, the slower devices on the bus, i.e., the Flash SIMM, ATM UNI M/P interface, BCSR and the external tool bus are buffered, while the SDRAM devices are not buffered from the bus.

Buffers are provided over address and strobe (when necessary) lines while transceivers are provided for data. Use is done with 74ALVT buffers (by Philips) which are 3.3V operated and 5V tolerantA and provide bus hold to reduce pull-up/pull-down resistors count (as required by the MSC8101). This type of buffers reduces noise on board due to reduced transition’s amplitude.

To further reduce noise and reflections, serial damping resistors may be added are placed over SDRAM address and all MSC8101 strobe lines.

The data transceivers are open only if there is an access to a validB buffered board address or during Hard - Reset configurationC. That way data conflicts are avoided in case an unbuffered memory read or off-board memory is read - provided that it is not mapped to an address valid on board. It is the users’ responsibility to avoid such errors.

5•5 Chip - Select Generator

The memory controller of the MSC8101 is used as a chip-select generator to access on-board (and off-board) memories, saving board’s area, reducing cost, power consumption and increasing flex- ibility. To enhance off-board application development, memory modules (including the BCSRx) may be disabled via BCSRD in favor of an external memory connected via the expansion connec- tors. That way, a CS line may be used off-board via the expansion connectors, while its associated local memory is disabled.

When a CS region, assigned to a bufferedE memory, is disabled via BCSR, the local data trans-

A. Required for Flash SIMM and BCSR

B. An address which is covered in a Chip-Select region, that controls a buffered device by BCSR logic. C. To allow a configuration word stored in the Flash memory or BCSR to become active.

D. After the BCSR is removed from the local memory map, there is no way to access it but to re-apply power to the MSC8101ADS.

MOTOROLA

MSC8101ADS RevB User’s Manual

43

For More Information On This Product,

Go to: www.freescale.com

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Contents MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Abbreviations’ List IntroductionRelated Documentation MSC8101ADS Specifications SpecificationCharacteristics Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9 Setting The Core Supply Voltage LevelSetting HReset Configuration Source Host I/F Operation OnCE Connection SchemeHost System Debug Scheme B Stand Alone OperationJTAG/OnCE Connector P6 34 +5V Power Supply ConnectionP6 JTAG/OnCE Port Connector Host I/F Connector P4Terminal to MSC8101ADS RS-232 Connection P4 Host I/F Connector38 10/100-Base-T Ethernet Port Connection Flash Memory Simm InstallationFlash Memory Simm Insertion Emulator Enable EE SW2 Host I/F Setting SW1Soft Reset Sreset Switch SW4 Abort Switch SW3Data Bus Width Setting SW5 & SW6 Power-On Reset Switch Preset SW8 Hard Reset Hreset Switch SW7Configuration Switch SW9 CPM Available Clock Mode SettingBoot Mode Select SW10 Modck432 JP2 Clock Buffer Set Software Options Switch SW11431 JP1 DLL Disable Jumpers434 JP4 VPP Source Selector 433 JP3 50 Ohm Enable436 JP6,JP7 MIC Enable 437 JP9 5V power supply for CodecLEDs ATM TX Indicator LD7 Ethernet Link Indicator LD4Fast Ethernet Clsn Indicator LD5 ATM RX Indicator LD6MSC8101’s Registers’ Programming System Initialization SIU Registers’ ProgrammingMemory Controller Registers Programming Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Manual Hard Reset Reset & Reset ConfigurationPower- On Reset Power On Reset ConfigurationHard Reset Configuration Word Summary Reset Configuration SchemesIRQ2 Manual Soft ResetClock Generator Local InterrupterChip Select Generator Bus BufferingMSC8101ADS Chip Select Assignments Bus Timing Machine Synchronous Dram BankSdram Programming MHz Sdram Mode Register ProgrammingSdram Flash Memory Simm Cycle Type \ Flash Delay nsecSdram Refresh Flash Programming Voltage Flash Simm Connection SchemeCommunication Ports MSC8101 I/O Ports/Name Ports Function Enable582 100/10 Base T Port 581 ATM PortAudio Codec CS4221 Programming5831 CS4221 Programming 584 T1/E1 Ports CS4221 Programming585 RS232 Ports Host I/F DMA off-board tool Host I/F Interconnect signalsBoard Control & Status Register Bcsr PON ATT DEF Hostcsp BCSR0 DescriptionBCSR0 Board Control / Status Register BIT Mnemonic10. BCSR1 Description BCSR0 DescriptionBCSR1 Board Control / Status Register Fethrst 10. BCSR1 DescriptionPON ATT DEF Atmrst Fethien12. BCSR2 Description 11. Peripheral’s Availability DecodingBCSR2 Board Control / Status Register BCSR3 Board Status Register 12. BCSR2 Description13. Flash Presence Detect 75 Encoding 14. Flash Presence Detect 41 Encoding15. BCSR3 Description Engineering 16. EXTOOLI03 Assignment17. External Tool Revision Encoding 18. ADS Revision EncodingPPC Bus Memory Map MSC8101ADS Memory Map FF800000 Ffffffff MSC8101ADS Memory MapFE000000 Ffffffff FF000000 FfffffffADS Power Scheme Power rails713 5V Bus Off-Board Application Maximum Current Consumption711 5V Bus 712 3V BusAppendix a MSC8101 Bill of Material Table A-1. MSC8101ADS Bill Of Material A1 BOMFreescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information B11 Interconnect SignalsTable B1-2. P1 System Expansion Interconnect Signals TSTAT2 TSTAT3 TSTAT4 TSTAT5 GNDTSTAT0 TSTAT1Damage to the PM5350 ATM UNI ClkxEXPD3 EXPD0EXPD1 EXPD2EXPCTL0 B12 MSC8101ADS’s P2 CPM Expansion Connector Table B1-3. P2 CPM Expansion Interconnect SignalsSCC1RXD PD30 PD7 SPICLKPD18SPIMOSIPD17 HwrdsAtmrca PA26 Atmtsoc PA29Atmrsoc PA27 AtmrfclkATMRXD4 PA14 ATMRXD7 PA17ATMRXD6 PA16 ATMRXD5 PA15Fethcrs PB26 Fethtxen PB29Fethrxer PB28 Fethcol PB27HD3 HD0HD1 HD2Fethmdc PC13 Atmfclk PC26SMCTX1PC5 Fethmdio PC12PC7 PC6B14 P4 Host Interface Connector Table B1-4. P3 ISP Connector Interconnect SignalsB13 Hreq HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9HA1 HA2 HA3 HCS1 HackHDS Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors B16B19 P17,P18 Double RJ45 T1/E1 Line Connectors Table B1-7. P12 Ethernet Port Interconnect SignalsB17 P12 Ethernet Port Connector B18 P15,P16 SMB ConnectorsB111 P20,P22,P23,P25 RCA Jack Connectors B110 P19,P21,P24 Stereo Phone Jack ConnectorsB113 P27A,B RS232 Ports’ Connectors Table B1-10. P27A Interconnect SignalsTable B1-11. P27B Interconnect Signals B112 P26 5V Power Supply ConnectorsFreescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc C11 First Include File Logic EquationsC12 Second Include file C13 Main File Constant Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant EE45HOLDVALUE Constant SIZE1HRESET~ Bidir Constant TCPCDEFAULT0 Constant TCPCDEFAULT1HDIMDEN~ Host SW Enable RSTCNF~ Output SRESET~HRRQEN~ SBOOTENOUT~SPARE1 Output HDIEN~WDTIMER4 WDTIMER1WDTIMER2 WDTIMER3Scndcfgbyteread Thirdcfgbyteread Fourthcfgbyteread EepromenableResets Cleartowdctrl BCSR1 SBOOTEN~BCSR3PONDEF0..SIZE3 BCSR3IRQ0 BCSR1PONDEF0..SIZE1END Defaults Begin DefaultsBCSR0 BCSR0PONCONST0..5 Else EEDPONDEFAULT,RSV37PONDEFAULTEND if END Generate END if EE PinsRegularpoweronreset = RPORI~ == Regularponresetactive PSDVAL~ = OpndrnvccEND if Else If Hdds thenIf !HDSP then Hdiwr = Else Hdiwr =Elsif MPCWRITEBCSR6 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR5 thenIf MPCREADBCSR0 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenElsif MPCREADBCSR3 then Elsif Scndcfgbyteread then HRESET~ =SRESET~ = Elsif Firstcfgbyteread thenEND if If !T1234EN~ & FETHIEN~ then Then SIGLAMP0OUT~ = GND ElseThen SIGLAMP1OUT~ Else SIGLAMP1OUT~116 Watchdog for Auto Reconfiguration END if Drive Poreset Impulse Reconfig Using BCSR4MODCK1-3 Driven 118
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