Nortel Networks MSC8101 ADS Flash Memory Simm, Cycle Type \ Flash Delay nsec, Sdram Refresh

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Functional Description

b. Two clocks latency setting is programmed for 50MHz Bus Clock

c. 8 beat burst is programmed for 32bit Data Bus width (Host Interface is active)

5•6•2 SDRAM Refresh

The SDRAM is refreshed using its auto-refresh mode. I.e., using SDRAM machine 1’s periodic timer, an auto-refresh command is issued to the SDRAM every 14 ∝sec, so that all 4096A SDRAM rows are refreshed within spec’d 57.3 msec, while leaving a 6.6msec interval of refresh redundancy within that window, as a safety measure, covering for possible delays in bus availability for the refresh controller.

5•7 Flash Memory SIMM

The MSC8101 is provided with 8Mbyte of 90 nsec flash memory SIMM, the SM73228XG1JHBGO by Smart Modular Technology which is composed of four LH28F016SCT-L95 chips by Sharp, arranged as 2M X 32 in a single bank. Support is given also to 16MBytes and 32 MBytes Simm’s. The Flash SIMM resides on an 80 pin SIMM socket and is buffered from the 60X bus to reduce capacitive load over it.

To minimize use of MSC8101s’ chip-select lines, only one chip-select line CS0 is used to select the Flash as a whole, while distributing chip-select lines among the module’s internal banks is done by on-board programmable logic (BCSR), according to the Presence-Detect lines of the Flash SIMM inserted to the MSC8101ADS.

The access time of the Flash memory provided with the MSC8101ADS is 95 nsec, however, devices with different delay are supported as well. By reading the delay section of the Flash SIMM Presence-Detect lines see TABLE 5-13. "Flash Presence Detect (7:5) Encoding" on page 59, the debugger can establish via register OR0 the correct number of wait-states needed to access the Flash SIMM (considering default system clock frequency).

The control over the Flash is done with the GPCM and a dedicated CS0 region which controls the whole bank. During hard - reset initializationB, the debugger or any application S/W for that matter, reads the Flash Presence-Detect lines via BCSR and determines how to program registers BR0 & OR0, within which the size and the delay of the region are determined. The performance of the flash memory is shown in TABLE 5-5.:

TABLE 5-5. Flash Memory Projected Performance Figures

 

Number of System Clock Cycles

 

@ 100 MHz Bus Clock Freq.

 

 

Cycle Type \ Flash Delay [nsec]

95

 

 

Read Access

10a

Writeb Access

10a

a. From TS asserted. However, due to internal activity, these figures may be larger.

b. The figures in the table refer to the actual write access. The write operation continues internally and the device has to be polled for completion.

The Flash connection scheme is shown in FIGURE 5-3:

A. In fact each SDRAM component is composed of 4 internal banks each having 4096 rows, but they are re- freshed in parallel.

B. i.e., initialization that follow the hard reset sequence at system boot.

46MSC8101ADS RevB User’s Manual MOTOROLA

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Contents MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Abbreviations’ List IntroductionRelated Documentation MSC8101ADS Specifications SpecificationCharacteristics Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9 Setting The Core Supply Voltage LevelSetting HReset Configuration Source OnCE Connection Scheme Host I/F OperationStand Alone Operation Host System Debug Scheme B34 +5V Power Supply Connection JTAG/OnCE Connector P6Host I/F Connector P4 P6 JTAG/OnCE Port ConnectorP4 Host I/F Connector Terminal to MSC8101ADS RS-232 ConnectionFlash Memory Simm Installation 38 10/100-Base-T Ethernet Port ConnectionFlash Memory Simm Insertion Host I/F Setting SW1 Emulator Enable EE SW2Soft Reset Sreset Switch SW4 Abort Switch SW3Data Bus Width Setting SW5 & SW6 Power-On Reset Switch Preset SW8 Hard Reset Hreset Switch SW7Configuration Switch SW9 Modck Available Clock Mode SettingBoot Mode Select SW10 CPMJumpers Software Options Switch SW11431 JP1 DLL Disable 432 JP2 Clock Buffer Set437 JP9 5V power supply for Codec 433 JP3 50 Ohm Enable436 JP6,JP7 MIC Enable 434 JP4 VPP Source SelectorLEDs ATM RX Indicator LD6 Ethernet Link Indicator LD4Fast Ethernet Clsn Indicator LD5 ATM TX Indicator LD7MSC8101’s Registers’ Programming System Initialization SIU Registers’ ProgrammingMemory Controller Registers Programming Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Power On Reset Configuration Reset & Reset ConfigurationPower- On Reset Manual Hard ResetSummary Reset Configuration Schemes Hard Reset Configuration WordManual Soft Reset IRQ2Local Interrupter Clock Generator Bus Buffering Chip Select GeneratorSynchronous Dram Bank MSC8101ADS Chip Select Assignments Bus Timing MachineSdram Programming MHz Sdram Mode Register ProgrammingSdram Flash Memory Simm Cycle Type \ Flash Delay nsecSdram Refresh Flash Simm Connection Scheme Flash Programming VoltageCommunication Ports Ports Function Enable MSC8101 I/O Ports/Name581 ATM Port 582 100/10 Base T PortAudio Codec CS4221 Programming5831 CS4221 Programming 584 T1/E1 Ports CS4221 Programming585 RS232 Ports Host I/F DMA off-board tool Host I/F Interconnect signalsBoard Control & Status Register Bcsr BIT Mnemonic BCSR0 DescriptionBCSR0 Board Control / Status Register PON ATT DEF Hostcsp10. BCSR1 Description BCSR0 DescriptionBCSR1 Board Control / Status Register Fethien 10. BCSR1 DescriptionPON ATT DEF Atmrst Fethrst12. BCSR2 Description 11. Peripheral’s Availability DecodingBCSR2 Board Control / Status Register 14. Flash Presence Detect 41 Encoding 12. BCSR2 Description13. Flash Presence Detect 75 Encoding BCSR3 Board Status Register15. BCSR3 Description 18. ADS Revision Encoding 16. EXTOOLI03 Assignment17. External Tool Revision Encoding EngineeringPPC Bus Memory Map MSC8101ADS Memory Map FF000000 Ffffffff MSC8101ADS Memory MapFE000000 Ffffffff FF800000 FfffffffPower rails ADS Power Scheme712 3V Bus Off-Board Application Maximum Current Consumption711 5V Bus 713 5V BusAppendix a MSC8101 Bill of Material A1 BOM Table A-1. MSC8101ADS Bill Of MaterialFreescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information Interconnect Signals B11Table B1-2. P1 System Expansion Interconnect Signals TSTAT1 GNDTSTAT0 TSTAT2 TSTAT3 TSTAT4 TSTAT5Clkx Damage to the PM5350 ATM UNIEXPD2 EXPD0EXPD1 EXPD3EXPCTL0 B12 MSC8101ADS’s P2 CPM Expansion Connector Table B1-3. P2 CPM Expansion Interconnect SignalsSCC1RXD PD30 Hwrds SPICLKPD18SPIMOSIPD17 PD7Atmrfclk Atmtsoc PA29Atmrsoc PA27 Atmrca PA26ATMRXD5 PA15 ATMRXD7 PA17ATMRXD6 PA16 ATMRXD4 PA14Fethcol PB27 Fethtxen PB29Fethrxer PB28 Fethcrs PB26HD2 HD0HD1 HD3Atmfclk PC26 Fethmdc PC13PC6 Fethmdio PC12PC7 SMCTX1PC5B14 P4 Host Interface Connector Table B1-4. P3 ISP Connector Interconnect SignalsB13 Hack HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9HA1 HA2 HA3 HCS1 HreqB16 Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors HDSB18 P15,P16 SMB Connectors Table B1-7. P12 Ethernet Port Interconnect SignalsB17 P12 Ethernet Port Connector B19 P17,P18 Double RJ45 T1/E1 Line ConnectorsB110 P19,P21,P24 Stereo Phone Jack Connectors B111 P20,P22,P23,P25 RCA Jack ConnectorsB112 P26 5V Power Supply Connectors Table B1-10. P27A Interconnect SignalsTable B1-11. P27B Interconnect Signals B113 P27A,B RS232 Ports’ ConnectorsFreescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc Logic Equations C11 First Include FileC12 Second Include file C13 Main File Constant SIZE1 Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant EE45HOLDVALUE ConstantSRESET~ Constant TCPCDEFAULT0 Constant TCPCDEFAULT1HDIMDEN~ Host SW Enable RSTCNF~ Output HRESET~ BidirHDIEN~ SBOOTENOUT~SPARE1 Output HRRQEN~WDTIMER3 WDTIMER1WDTIMER2 WDTIMER4BCSR1 SBOOTEN~ EepromenableResets Cleartowdctrl Scndcfgbyteread Thirdcfgbyteread FourthcfgbytereadBCSR1PONDEF0..SIZE1 BCSR3IRQ0 BCSR3PONDEF0..SIZE3END Defaults Begin DefaultsBCSR0 BCSR0PONCONST0..5 Else EEDPONDEFAULT,RSV37PONDEFAULTEND if END Generate PSDVAL~ = Opndrnvcc EE PinsRegularpoweronreset = RPORI~ == Regularponresetactive END ifElse Hdiwr = If Hdds thenIf !HDSP then Hdiwr = END if ElseElsif MPCWRITEBCSR5 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR6 thenIf MPCREADBCSR0 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenElsif MPCREADBCSR3 then Elsif Firstcfgbyteread then HRESET~ =SRESET~ = Elsif Scndcfgbyteread thenElse SIGLAMP1OUT~ Then SIGLAMP0OUT~ = GND ElseThen SIGLAMP1OUT~ END if If !T1234EN~ & FETHIEN~ then116 Watchdog for Auto Reconfiguration END if Drive Poreset Impulse Reconfig Using BCSR4MODCK1-3 Driven 118
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