Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
Functional Description
5•1•5 MSC8101 Internal Hard Reset Sources
The MSC8101 has internal sources which generate Hard / Soft Resets. Among these sources are:
1)Loss of Lock Reset (Hard)
2)S/W Watch Dog Reset (Hard)
3)Bus Monitor (Hard)
4)JTAG/ONCE Reset (Hard)
In general, the MSC8101 asserts a reset line HARD or SOFT for a period 512 clock cycles after the reset source has been identified. A hard reset sequence is followed by a soft reset sequence that released three bus clocks later than hard reset is negated.
5•2 Local Interrupter
There are external interrupts which are applied to the MSC8101ADS via its interrupt controller:
1)ABORT (NMI)
2)ATM UNI interrupt
5•2•1 ABORT Interrupt
The ABORT (NMI), is generated by a
5•2•2 ATM UNI Interrupt
To support ATM UNI (User Network I/F) event report by means of interrupt, the interrupt output of the UNI (INTB) is connected to IRQ6 line of the MSC8101.
Since INTB of the UNI is an
5•2•3 QFALC Interrupt
Interrupt of T1/E1 Frame are served by IRQ7. The QFALC has an
5•3 Clock Generator
The MSC8101 requires a single clock source for the main clock oscillator. Use is done with 25MHz (16.38MHz) 3.3V clock generator mounted on the
Special care is taken to isolate and terminate the clock route between the
42 | MSC8101ADS RevB User’s Manual | MOTOROLA |
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