Texas Instruments TLV1562 manual The Serial DAC/DSP System, DSP/DAC Interconnection

Page 15

4 The Serial DAC/DSP System

The Serial DAC/DSP System

4 The Serial DAC/DSP System

The software configures the buffered DSP serial port to the 16-bit master mode so that the DSP generates the frame sync signal at BFSX and the data clock at BCLKX serial port terminals. Table 4 shows the connections between the DSP and the DAC TLC5618A.

Table 4. DSP/DAC Interconnection

FROM DSP	TO DSP	TO DAC

BFSX	BFSR	CS

BCLKX	CLKR	I/O CLK

BDX	BDR	DATA IN

The following statements describe the generation and application of the configuration and control signals.

•The DSP BCLKX output provides a 20-MHz data clock, which is a divide-by-2 of the DSP master clock.

•The DSP BDX output supplies the 16-bit control and data move to the TLC5618A at DATA IN.

•The DSP BFSX frame synchronization signal, connected to CS, triggers the start of a new frame of data.

After the falling edge of FSX, the next 16 data clocks transfer data into the DSP DR terminal and out of the DX terminal. Since this DSP/DAC interface is synchronous, the FSX signal is sent to the FSR terminal, and the CLKX is sent to the CLKR terminal.

Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP

9

Image 15

Contents TParalInteMS3rflelADConvertertotheacing20C54xDSPtheTLV1562 JulySLAA040 Application ReportIMPORTANT NOTICE Contents 8.5.5 List of Figures List of TablesFigures viSLAA040 2.1 TMS320C54x Starter Kit Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP1 Introduction 2 The Board2.3.1.1 The Universal Interface 2.2 TLV1562EVM2.3 ADC TLV1562 Overview 2.3.1 Suggestions for the ’C54x to TLV1562 InterfaceUsing RD or the CSTART Signal to Start Conversion 2.3.2 Recyclic ArchitectureFigure 2. TLV1562 to ’C54x DSP Interface of the EVM 2.3.3 Note on the Interface, Using an External ADC Clock Drive 2.4 Onboard Components2.4.1 TLC5618A - Serial DAC 2.4.2 THS5651 - Parallel Output CommsDAC Figure 3. TLC5618A to ’C542 DSP InterfaceFigure 4. THS5651 to C542 DSP Interface 3 Operational Overview 3.1 Reference Voltage Inputs3.2 Input Data Bits 3.3 Connections Between the DSP and the EVM Table 1. Signal Connections8SLAA040 3.3.1 Jumpers Used on the TLV1562EVMTable 2. 3-Position Jumpers Table 3. 2-Position JumpersTable 4. DSP/DAC Interconnection 4 The Serial DAC/DSP System5 The DSP Serial Port Table 5. DSP Serial Port Signals and Registers6.1 DSP Internal Serial Port Operation 6 Other DSP/TLV1562 SignalsTable 6. DSP Algorithm for Writing to the ADC 7.2 Mono Interrupt Driven Mode Using RD7 Conversation Between the TLV1562 and the DSP 7.1 Writing to the ADCTable 7. DSP Algorithm for Mono Interrupt Driven Mode Using RD tDCSL-sample+1ADCSYSCLKtENDATAOUT = 41 ns 7.3 Mono Interrupt Driven Mode Using CSTART Table 8. DSP Algorithm for Mono Interrupt Driven Mode Using CSTART14 SLAA040 Table 9. DSP Algorithm for Dual Interrupt Driven Mode 7.4 Dual Interrupt Driven Mode7.5 Mono Continuous Mode Table 10. DSP Algorithm for Mono Continuous Mode16 SLAA040 Table 11. DSP Algorithm for Dual Continuous Mode 7.6 Dual Continuous Mode8 Software Overview 8.1 Software Development tools8.2 DSP Memory Map Figure 5. Memory Map 8.3.2 Address and Data Bus for I/O Tasks 8.3.3 Timer Output8.3 Programming Strategies for the ’C54x, Explanations 8.3.1 Optimizing CPU Resources for Maximum Data Rates8.3.5 Generating the Chip Select Signal and the CSTART Signal 8.3.4 Data Page Pointer8.3.6 Interfacing the Serial DAC 5618A to the DSP MARK DP = #1 ARP = #5 8.3.7 Interrupt Latency8.3.8 Branch Optimization goto/dgoto, call/dcall GOTO MARK8.3.9 Enabling Software Modules .if/.elseif/.endif 8.4 Software Code Explanation8.4.1 Software Principals of the Interface Disadvantage 8.4.1.2 Timed Solution8.4.1.1 Software Polling AdvantageDisadvantages 8.4.1.3 Interrupt Driven Solution8.4.1.5 Setting the Right Switches AdvantagesTable 12. Switch Settings TaskTable 13. Instruction in the Program Header Step 8.4.1.6 Common Software for all Modes 8.5 Flow Charts and Comments for All Software Modes8.5.1 The Mono Interrupt Driven Mode Using RD to Start Conversion Table 14. Instruction in the Program Header Stepcommon file of all modes constants definition Program FilesOther Files Code verificationFigure 6. Software Flow of the Mono Interrupt Driven Solution Common file of all modes constants definition 8.5.2 Mono Interrupt Driven Mode Using CSTART to Start ConversionCalibration procedure of the DAC Includes the complete software algorithm to control the monomodePull Down CSTART Initialize SPISAVE Poll INTO Pin Until h/0 Transition OccursThis only works for one TLV1562 not multiple because CS is not used 8.5.2.1 Throughput Optimization†8.5.3 Dual Interrupt Driven Mode Figure 8. Time Optimization monocst1Maximum Performance at 1.2 MSPS with Internal Clock IMPORTANT NOTE The code has been optimized to maximize the data throughput. It was found that CSTART can be pulled low earlier than the data read instruction is performed by the DSP. This saves the 100-ns wait time in STEP 3 because the data read requires at least 100 ns. Therefore, CSTART gets pulled high directly after data read, and the interface becomes faster and gains throughput. This variation will be found in the code. The data acquisition is done in a small number of steps that explains everything inside the code Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 8.5.4 Mono Continuous Mode Figure 10. Flow Chart Mono Continuous Mode 8.5.5 Dual Continuous Mode Figure 11. Flow Chart Dual Continuous Mode Program Files 8.6 Source Code 8.6.1 Common Software for all Modes except C-Callable8.6.1.1 Constants.asm 42 SLAA040 set 000C0h Operate without calibrated inputs no offset8.6.1.2 Interrupt Vectors 44 SLAA040 4C internal timer interrupttitle ”COMMAND FILE FOR TLV1562.ASM” 8.6.1.3 linker,cmd8.6.1.4 Auto.bat File Linker.lnk COMMAND FILEcounter for one channel Mainprogram Monomode.asmpointer address when using any of the following variables jump address to init. new channelsent value to register CR0 of the ADC if SENDOUTSERIAL endif if INT0DRIVENPOLLINGDRV48 SLAA040 endif elseif INT0DRIVEN if AUTOPWDNENABLEendif if DIFFINPUTMODE = bit*AR5,15-0elseif NOINT0SIG 52 SLAA040 CALIBRAT.ASM 8.6.3 Calibration of the ADC54 SLAA040 if SMECALIBRATION 56 SLAA040 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 58 SLAA040 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 60 SLAA040 if INT0DRIVENPOLLINGDRV 62 SLAA040 = bit*AR5,15-0 64 SLAA040 endif if SAVEINTOMEMORYSoftware Overview Mainprogram DUALIRQ1.asm 8.6.5 Dual Interrupt Driven ModeConstants definition - see 8.6.1.1 Constants.asm Interrupt Routine handler - see 8.6.1.2 Interrupt VectorsInterfacing the TLV1562 Parallel ADC to the TMS320C54x DSP Software Overviewif SENDOUTSERIAL Software OverviewSoftware Overview 70 SLAA040 if POLLINGDRV 72 SLAA040 endif 8.6.6 Mono Continuous Mode Mainprogram MONOCON1.asm74 SLAA040 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 76 SLAA040 endif if EXTERNALCLOCK 78 SLAA040 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 8.6.7 Dual Continuous Mode Mainprogram DUALCON1.asm80 SLAA040 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 82 SLAA040 endif 84 SLAA040 Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 80h samples of channel 1 will be stored beginning on 2000h 8.6.8 C-CallableMainprogram C1562.c TLV1562Channel, Save Memory Start address, NUMBEROFSAMPLESInterfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 88 SLAA040 AR7+ = data@ADSAMPLE 90 SLAA040 Vectors.asmint2 returnenable 48 external interrupt int2 nop Auto.bat Linker.cmd92 SLAA040 10 References 9 Summary