Texas Instruments TLV1562 manual Software Polling, Advantage, Disadvantage, Timed Solution

Software Overview

8.4.1.1Software Polling

The status of the input pin is tested in a loop until the valid transition occurs. After this transition, the program branches to the next instruction (reads data sample).

Advantage:

•Relatively fast program response after high-to-low transition of INT

•The software compensates for variations of timing given in data sheets for conversion and the real time until the flag goes high.

•Not critical for any software changes (e.g. adding new features)

•Even when the program reaches the polling loop later than the transition occurred, it steps ahead properly.

Disadvantage:

•Time inside the polling loop is not usable for other software features (wasted CPU power)

•A hang up (ADC does not respond) will not be recognized without a watchdog algorithm

•The polling algorithm requires five instruction cycles. Depending on when the conversion finishes during these five instructions (when the INT signal goes low), the time response after the falling edge can vary up to the five instruction cycles. As experiments confirmed, this can result in a variation in the length of the sampling window. So, a filter algorithm (eg. FFT) on the samples might result in slightly different results for a steady (stable) input function, related to the sampling time variations. The only way to prevent this is to control the conversion with the on-chip timer of the DSP. Unfortunately, the maximum throughput falls off with increased requirements for CPU power.

8.4.1.2Timed Solution

How long the ADC requires for conversion must be factored into the software flow. In other words, the DSP has to wait a certain time between initializing the conversion and reading the conversion result on the data bus from the ADC. This timing is critical to the sampling device. If the conversion time of a data converter changes (data sheet), the timing must be verified again.

Advantage:

•Fastest solution (with a fine tune, the maximum performance can be extracted from the converter)

•Saves CPU power of the DSP (no time wasted for polling)

•Program can not hang up in an endless loop

•Less hardware required (input pin on the DSP and INT connection are left out)

Disadvantage:

•Every software variation changes timing and therefore, requires fine tuning again. This can be avoided by using the DSP timer module, but since the TLV1562 is an extremely fast device (2 MSPS at 10 bit), a timer module solution becomes too slow.

•If the conversion time of the ADC varies for some reasons, this algorithm is not able to respond; instead, the maximum conversion time is used.

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