Texas Instruments manual Conversation Between the TLV1562 and the DSP, Writing to the ADC

Conversation Between the TLV1562 and the DSP

7 Conversation Between the TLV1562 and the DSP

The complexity of the TLV1562 ADC may be confusing because of the number of possible modes to drive the protocol between DSP and ADC. The following paragraphs explain more about the data sheet descriptions for interfacing the ’C54x to the ADC.

7.1Writing to the ADC

Registers CR0 and CR1 must be set to choose any of the modes the TLV1562 offers. Therefore, a write sequence must be performed from the DSP to the ADC.

After selecting the ADC (CS low), a high-low transition of the WR line tells the converter that something is to be written to the data port.

Table 6. DSP Algorithm for Writing to the ADC

STEPS				TIMING, NOTES
1.	Set one DSP I/O waitstate			Make timing between 40 MHz C54x CPU compatible with the TLV1562
2.	Clear			Select ADC
			CS
3.	Send out data on the bus			The signal		is automatically handled by the DSP
					WR
4.	Set			Deselect ADC
		CS

7.2Mono Interrupt Driven Mode Using RD

This mode is used when the application needs to sample one channel at a time and performs the sampling, conversion, and serial transmission steps only once. Although this mode produces continuous sampling data, the use of other modes is recommended. One reason is the CS signal has to stay low during the whole sampling/conversion time. An interesting advantage of this mode is its ability to control the start-sample time.

The RD signal controls the sampling and converting. Every falling edge of RD stops the sampling process (disconnects the capacitor from the input signal) and starts the signal conversion. After two ADCSYSSCLKs, the sampling capacitor gets connected back to the input signal to do the next sampling. The conversion time needs five ADCSYSCLKs to finish the conversion before it gets written to the data port.

During configuration, the rising edge of WR starts the sampling.

Also, when conversion is finished, the ADC clears the INT signal purposes. Next the ADC writes the conversion result to the data port. The rising edge of RD resets this status; in other words, the INT signal goes back to logic high and the conversion result on the data port becomes invalid (the ADC data port gets 3-stated).

The configuration data needs to be written only once to the ADC. After this, toggling the RD signal runs the ADC in a sampling/conversion/sending mode and the RD signal releases every new cycle.

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