Software Overview
8.3Programming Strategies for the ’C54x, Explanations
Before listing the program code, this chapter introduces some basic instructions (strategies) to provide the ’C54x user with some ideas for dealing with the DSP architecture.
8.3.1Optimizing CPU Resources for Maximum Data Rates
The ’C54x processor on the DSKplus starter kit runs at an internal clock frequency of 40 MHz. Since the pipeline architecture allows most instructions to be executed in one cycle, the DSP provides up to 40 MIPS. However, some instructions, especially branch instructions, are not single cycle instructions; therefore, they lower the available CPU power. Because of the high transfer rate of the TLV1562 ADC, the software code must be optimized to test the full ADC performance. Since correct signal timing between DSP and ADC requires some instructions per sample, the CPU power required between two samples is very small.
The optimum case is to read a new sample, store it into memory, execute a customized task as it could be data filtering (FFT, FIR, IIR), and send a digital result to one of the DACs. Unfortunately, this task is impossible at the ADC’s maximum throughput of 40 MIPS. Therefore, this software only stores the samples and optionally moves them out to the DACs. Enabling all options at the same time prevents the application from running at maximum throughput.
The following switches enable/disable these actions:
SAVE_INTO_MEMORY .set 00001h; set 1 to store the samples into memory SEND_OUT_SERIAL .set 00001h; set 1 to send last sample to the serial DAC SEND_OUT_PARALLEL .set 00001h; set 1 to send last sample out to the parallel DAC
8.3.2Address and Data Bus for I/O Tasks
8.3.2.1Writing
PORT(PA) = Smem
Writing something to the I/O bus uses the port instruction. PA sets the ADDRESS bus permanently to that value. Smem is a value from memory, transferred for one clock cycle to the DATA bus.
@send = #01234h ; set the content of memory address send to 1234h
port(0FFFFh) = @send ; set address bus to FFFFh and write 1234h for one cycle ; on the DATA bus
8.3.2.2Reading
Smem = PORT(PA)
Reading from the I/O bus. PA sets the ADDRESS bus. Smem is a memory cell, PA the address on the bus.
8.3.3Timer Output
@TCR | = #00010h | ; deactivate timer |
@PRD | = #00000h | ; |
@TCR | = #00C01h | ; set timer output toggling frequency to CLKOUT |
|
| ; frequency ; and start toggling |
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