VXI SVM2608 user manual Accessing the Registers, Description of Registers, Sysfailctl

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VXI Technology, Inc.

The binary values are then converted into a hexadecimal format:

Binary

Hexadecimal

0000 0000 0110 0010

0x0062

This determines the data value required for the aforementioned settings.

ACCESSING THE REGISTERS

With both D16 and D32 data transfer available, the user can write either 16 or 32 bits of data to the registers. To change the settings of the module, it is only necessary to write a 16- or 32-bit integer to the specified register with the new configuration.

All registers, as defined in the following section, are 16-bit registers. A 32-bit write can be made to registers that are located in consecutive addresses. The consecutive 16-bit registers that can be accessed as 32-bit registers are:

 

Sample Rate Register (0x0C, 0x34, 0x5C, 0x84, 0xAC, 0xD4)

 

Sample Points Register (0x10, 0x38, 0x60, 0x88, 0xB0, 0xD8)

 

Pre-Trigger Points Register (0x14, 0x3C, 0x64, 0x8C, 0xB4, 0xDC)

 

Trigger Delay Register (0x18, 0x40, 0x68, 0x90, 0xB8, 0xE0)

 

FIFO data (0x24, 0x4C, 0x74, 0x9C, 0xC4, 0xEC)

 

Result Register (0x28 & 0x2C, 0x50 & 0x54, 0x78 & 0x7C, 0xA0 & 0xA4, 0xC8 &

 

0xCB, 0xF0 & 0xF4)

 

 

NOTE

Reading 32 bits from a 16-bit register may generate a BERR on the VME bus.

 

Writing 32 bits to a 16-bit register may generate a BERR on the VME bus or may corrupt data in

 

another register.

DESCRIPTION OF REGISTERS

The following pages describe the registers found in the SVM2608 Register Map for A32 address space that starts at 0x00C0000. When multiple channels registers have the same functions, the offsets appear in parenthesis separated by commas with Channel 0 being listed first, followed by Channel 1, etc. For example, the description used by the Control Register Bit is applicable to all six channels at offsets 0x08 for Channel 0, 0x30 for Channel 1, 0x58 for Channel 2 and 0x80 for Channel 3, 0xA8 for Channel 4 and 0xD0 for Channel 5. This is indicated in the register description by using the following notation: (0x08, 0x30, 0x58, 0x80, 0xA8, 0xD0). Unless otherwise noted, register descriptions apply to all channels (Channels 0 – 5).

Reset, Sys Fail Control, Interrupt Levels Register (0x00) — Read & Write

D15

Unused

This bit is reserved for future use.

 

 

System Fail Control - This bit controls whether or not the sysfail line

 

 

will be masked.

D14

SYSFAILCTL

0

= Card can assert sysfail line.

 

 

 

 

1

= Sysfail line is masked and card cannot assert sysfail line.

 

 

Pon state = 0

D13 – D3

Unused

These bits are reserved for future use.

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SVM2608 Programming

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Contents SVM2608 VXI Technology, Inc Table of Contents Self Test Command Warranty Limitation of WarrantyCertification Restricted Rights LegendEMC Steve Mauga, QA ManagerService should only be performed by qualified personnel Terms and SymbolsUse Proper Power Cord Use Proper Power SourceAvoid Electric Shock Ground the ProductOperating Conditions Improper UseVXI Technology World Headquarters VXI Technology Cleveland Instrument DivisionVXI Technology Lake Stevens Instrument Division Technical SupportVXI Technology, Inc SVM2608 Preface Introduction OverviewScale Acquiring Data TriggeringPre-Trigger Linear ModeDelayed Trigger Fifo Mode CommandsCalibrations Test BusOption SVM2608 Block Diagram SVM2608 Environmental Specifications Physical DescriptionFront Panel Interface Wiring GND CH1I CH3IGND CH1I+ GND CH3I+ Exttrigin CH0I CH2ISVM2608 Specifications MtbfOption 1 SVM2608-01 VXI Technology, Inc SVM2608 Introduction Calculating System Power and Cooling Requirements Setting the Chassis Backplane JumpersSetting the Base Address Rotary Switch LocationsMSB LSB ExampleDivide Decimal Switch to C and the front switch to Module INSTALLATION/REMOVALDevice Memory Maps Function OffsetReserved Register OffsetSVM2608 A32 Register MAP MS = Most Significant LS = Least Significant0x72 Command Register Channel 0x74 Databyte Ordering Determining the Register Address Sysfailctl Accessing the RegistersDescription of Registers Force Trigger, Start Register 0x02 Read & Write INTLVL2HSTRIGSRC2 EXT Trig SlopeExternal Trigger Level 0x06 Read & Write TimeoutctlReserved 2WIREOHMS 4WIREOHMSLINEAR/FIFO ATTN-GAIN1-GAIN0KHz Channels 0-3/5 MHz Channels 4-5 LPF Control This bit Sample Rate 0x0C, 0x34, 0x5C, 0x84 Read & WriteSample Rate 0x0E, 0x36, 0x5E, 0x86 Read & Write Sample Rate, High-Speed 0xAC, 0xD4 Read & Write Sample Rate, High-Speed 0xAE, 0xD6 Read & WriteTimeout 0x1C, 0x44, 0x6C, 0x94, 0xBC, 0xE4 Read & Write Reserved Registers 0xF8 0xFC Fifo Data 0x24, 0x4C, 0x74, 0x9C, 0xC4, 0xEC Read OnlyFifo Data 0x26, 0x4E, 0x76, 0x9E, 0xC6, 0xEE Read Only Trigger Delay = Microprocessor Commands Measurement CommandsCaptured Data Calculations Resistance Measurement Dynamic Method Self Test CommandResistance Measurement Offset Method Preset Setting Measurement Commands ExampleCalibration Commands Sample PointsSample Rate Trigger Event Forced TriggerPage Error Processing There are no errors in the queue Diagnostic Commands Changes become effective the next time the module powers up Example 2 Setting Channel 2 to Acquire 200,000 Samples ExamplesExample 3 Setting Channel 2 to Pre-acquire 100,000 Samples Timeout Counter = Timeout / Timeout Base Clock Timeout Register = Timeout Base * 213 + Timeout CounterVXI Technology, Inc SVM2608 Programming Appendix a Data Swapping ExampleVXI Technology, Inc SVM2608 Appendix a Index
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