VXI SVM2608 user manual Databyte Ordering

Page 30

VXI Technology, Inc.

OFFSET

WRITE FUNCTION

READ FUNCTION

0xB6

Pre-Trigger Points (Channel 4) – (LS)

Pre-Trigger Points (Channel 4) – (LS)

0xB8

Trigger Delay (Channel 4) – (MS)

Trigger Delay (Channel 4) – (MS)

0xBA

Trigger Delay (Channel 4) – (LS)

Trigger Delay (Channel 4) – (LS)

0xBC

Timeout (Channel 4)

Timeout (Channel 4)

0xBE

Interrupt Enable (Channel 4)

Interrupt Enable (Channel 4)

0xC0

Reserved

Interrupt Status (Channel 4)

0xC2

Command Register (Channel 4)

Command Register (Channel 4)

0xC4

Reserved

FIFO Data (Channel 4) – (MS)

0xC6

Reserved

FIFO Data (Channel 4) – (LS)

0xC8

Reserved

Result Register (Channel 4) – (MS)

0xCA

Reserved

Result Register (Channel 4) – (LS)

0xCC

Reserved

Result Register (Channel 4) – (MS)

0xCE

Reserved

Result Register (Channel 4) – (LS)

0xD0

Control (Channel 5)

Control (Channel 5)

0xD2

Trigger Level (Channel 5)

Trigger Level (Channel 5)

0xD4

Sample Rate (Channel 5) – (MS)

Sample Rate (Channel 5) – (MS)

0xD6

Sample Rate (Channel 5) – (LS)

Sample Rate (Channel 5) – (LS)

0xD8

Sample Points (Channel 5) – (MS)

Sample Points (Channel 5) – (MS)

0xDA

Sample Points (Channel 5) – (LS)

Sample Points (Channel 5) – (LS)

0xDC

Pre-Trigger Points (Channel 5) – (MS)

Pre-Trigger Points (Channel 5) – (MS)

0xDE

Pre-Trigger Points (Channel 5) – (LS)

Pre-Trigger Points (Channel 5) – (LS)

0xE0

Trigger Delay (Channel 5) – (MS)

Trigger Delay (Channel 5) – (MS)

0xE2

Trigger Delay (Channel 5) – (LS)

Trigger Delay (Channel 5) – (LS)

0xE4

Timeout (Channel 5)

Timeout (Channel 5)

0xE6

Interrupt Enable (Channel 5)

Interrupt Enable (Channel 5)

0xE8

Reserved

Interrupt Status (Channel 5)

0xEA

Command Register (Channel 5)

Command Register (Channel 5)

0xEC

Reserved

FIFO Data (Channel 5) – (MS)

0xEE

Reserved

FIFO Data (Channel 5) – (LS)

0xF0

Reserved

Result Register (Channel 5) – (MS)

0xF2

Reserved

Result Register (Channel 5) – (LS)

0xF4

Reserved

Result Register (Channel 5) – (MS)

0xF6

Reserved

Result Register (Channel 5) – (LS)

0xF8

Reserved

Reserved

0xFA

Reserved

Reserved

0xFC

Reserved

Reserved

0xFE

External Trigger Level for High-Speed Channel

External Trigger Level for High-Speed Channel

DATA(BYTE) ORDERING

When a pair of 16-bit registers is read as a 32-bit register, the content of the register marked MS is placed on the VME Bus on D31 - D16 and the content of the register marked LS is placed on D15 - D0. Similarly, when a pair of 16-bit registers is written as a 32-bit register, the register marked MS is loaded with the data present on the VME Bus on D31 - D16 and the register marked LS is loaded with the data present on D15 - D0. All other registers should be addressed as 16-bit registers to prevent any malfunctioning.

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SVM2608 Programming

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Contents SVM2608 VXI Technology, Inc Table of Contents Self Test Command Certification WarrantyLimitation of Warranty Restricted Rights LegendEMC Steve Mauga, QA ManagerUse Proper Power Cord Service should only be performed by qualified personnelTerms and Symbols Use Proper Power SourceOperating Conditions Avoid Electric ShockGround the Product Improper UseVXI Technology Lake Stevens Instrument Division VXI Technology World HeadquartersVXI Technology Cleveland Instrument Division Technical SupportVXI Technology, Inc SVM2608 Preface Introduction OverviewScale Acquiring Data TriggeringLinear Mode Delayed TriggerPre-Trigger Calibrations Fifo ModeCommands Test BusOption SVM2608 Block Diagram SVM2608 Environmental Specifications Physical DescriptionGND Front Panel Interface WiringGND CH1I CH3I CH1I+ GND CH3I+ Exttrigin CH0I CH2ISVM2608 Specifications MtbfOption 1 SVM2608-01 VXI Technology, Inc SVM2608 Introduction Calculating System Power and Cooling Requirements Setting the Chassis Backplane JumpersSetting the Base Address Rotary Switch LocationsExample Divide DecimalMSB LSB Switch to C and the front switch to Module INSTALLATION/REMOVALReserved Device Memory MapsFunction Offset Register OffsetSVM2608 A32 Register MAP MS = Most Significant LS = Least Significant0x72 Command Register Channel 0x74 Databyte Ordering Determining the Register Address Accessing the Registers Description of RegistersSysfailctl HSTRIGSRC2 Force Trigger, Start Register 0x02 Read & WriteINTLVL2 EXT Trig SlopeTimeoutctl ReservedExternal Trigger Level 0x06 Read & Write LINEAR/FIFO 2WIREOHMS4WIREOHMS ATTN-GAIN1-GAIN0Sample Rate 0x0C, 0x34, 0x5C, 0x84 Read & Write Sample Rate 0x0E, 0x36, 0x5E, 0x86 Read & WriteKHz Channels 0-3/5 MHz Channels 4-5 LPF Control This bit Sample Rate, High-Speed 0xAC, 0xD4 Read & Write Sample Rate, High-Speed 0xAE, 0xD6 Read & WriteTimeout 0x1C, 0x44, 0x6C, 0x94, 0xBC, 0xE4 Read & Write Fifo Data 0x24, 0x4C, 0x74, 0x9C, 0xC4, 0xEC Read Only Fifo Data 0x26, 0x4E, 0x76, 0x9E, 0xC6, 0xEE Read OnlyReserved Registers 0xF8 0xFC Trigger Delay = Microprocessor Commands Measurement CommandsCaptured Data Calculations Self Test Command Resistance Measurement Offset MethodResistance Measurement Dynamic Method Preset Setting Measurement Commands ExampleSample Rate Calibration CommandsSample Points Trigger Event Forced TriggerPage Error Processing There are no errors in the queue Diagnostic Commands Changes become effective the next time the module powers up Example 2 Setting Channel 2 to Acquire 200,000 Samples ExamplesExample 3 Setting Channel 2 to Pre-acquire 100,000 Samples Timeout Counter = Timeout / Timeout Base Clock Timeout Register = Timeout Base * 213 + Timeout CounterVXI Technology, Inc SVM2608 Programming Appendix a Data Swapping ExampleVXI Technology, Inc SVM2608 Appendix a Index
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