VXI Technology, Inc.
Force Trigger, Start Register (0x02) — Read & Write
D5 – D0
START5 – 0
Acquisition Armed - These bits control whether or not the specified channel is to be armed for an acquisition. A channel must remain ARMED for the entire duration of the acquisition process. Clearing an ARM bit will reset the internal
D0 for Channel 0
D1 for Channel 1
D5 for Channel 5
Having one bit per channel allows multiple channels to be triggered simultaneously.
0 = Channel not armed for acquisition
1 = Channel armed and ready for acquisition Pon state = 0
Reserved (0x04)
D15 – D0
Reserved
These bits are reserved for future use.
External Trigger Level (0x06) — Read & Write
D15 – D12 | Unused | These bits are reserved for future use. |
D11 – D0 | External Trigger Level | Sets the level at which the module triggers from an external source. |
Control Register (0x08, 0x30, 0x58, 0x80, 0xA8, 0xD0) — Read & Write
| D15 – D14 | Unused |
| These bits are reserved for future use. | |||
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| AC/DC Select - This bit selects between ac and dc coupling for high- | |
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| speed Channels 4 – 5. | |
| D13 |
| AC/DC Coupling |
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| 0 | = AC |
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| 1 = dc | |||
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| Pon state= 0 | |
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| Note: This bit is only utilized by | |
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| unused for Channels 0 – 3. | |
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| 1 MΩ /50 Ohms - Selects between the 1 MΩ and 50 Ω | |
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| 0 | = 1 MΩ | |
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| 1 | = 50 Ω | |
| D12 |
| 1 MΩ/50 Ω |
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| Pon state= 0 | |||
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Note: This bit is only utilized by
Timeout Control - This bit controls whether or not a timeout condition will cause the timeout bit to be set in the interrupt status register.
D11 | TIMEOUTCTL | 0 | = Disable timeout status bit |
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| 1 | = Enable timeout status bit |
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| Pon state = 0 |
34 | SVM2608 Programming |