VXI SVM2608 Force Trigger, Start Register 0x02 Read & Write, INTLVL2, HSTRIGSRC2, EXT Trig Slope

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Reset, Sys Fail Control, Interrupt Levels Register (0x00) — Read & Write

D2 – D0

INTLVL2 - 0

Interrupt Level - These bits determine the interrupt service level.

111 = Interrupt level 7

110 = Interrupt level 6

101 = Interrupt level 5

100 = Interrupt level 4

011 = Interrupt level 3

010 = Interrupt level 2

001 = Interrupt level 1

000 = No interrupt

Force Trigger, Start Register (0x02) — Read & Write

 

 

 

 

 

 

 

High-Speed Trigger Source – These bits select a trigger source for the

 

 

 

 

 

 

 

high-speed channels.

 

 

 

 

 

 

000

= Channel 0

 

 

 

 

 

 

001

= Channel 1

 

 

 

 

 

 

010

= Channel 2

 

D15 – D13

 

 

HS_TRIGSRC2 - 0

 

011

= Channel 3

 

 

 

 

100

= Invalid state

 

 

 

 

 

 

 

 

 

 

 

 

101

= Invalid state

 

 

 

 

 

 

110

= External

 

 

 

 

 

 

111

= Invalid state

 

 

 

 

 

 

 

Note: These bits are only utilized by high-speed Channels 4 and 5. These

 

 

 

 

 

 

 

bits are unused for Channels 0 – 3.

 

 

 

 

 

 

 

External Trigger Slope – This bit sets the slope of the external trigger

 

 

 

 

 

 

 

 

for low-speed Channels 0 - 3.

 

 

D12

 

 

EXT TRIG SLOPE

 

 

0 = Positive

 

 

 

 

 

 

1 = Negative

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: This bit is only utilized by high-speed Channels 4 and 5. This bit is

 

 

 

 

 

 

 

 

unused for Channels 0 – 3.

 

 

 

 

 

 

 

 

Force Trigger - All of the channels have the ability to be triggered via

 

 

 

 

 

 

 

software when in the arm mode. Acquisition begins when trigger is

 

 

 

 

 

 

 

forced. These bits need to be reset to ‘0’ in order to allow subsequent

 

 

 

 

 

 

 

triggers (it is the transition of a bit from 0 to 1 that forces a trigger). One

 

 

 

 

 

 

 

bit is assigned to each channel as follows:

 

 

 

 

 

 

 

D6 for Channel 0

 

 

 

 

 

 

 

D7 for Channel 1

 

D11 – D6

 

FTRIG5 - 0

 

 



 

 

 

 

 

 

 

 

D11 for Channel 5

 

 

 

 

 

 

 

Having one bit per channel allows multiple channels to be triggered

 

 

 

 

 

 

 

simultaneously.

 

 

 

 

 

 

 

0 = Do not force trigger

 

 

 

 

 

 

 

1 = Force software trigger

 

 

 

 

 

 

 

Pon state =0

SVM2608 Programming

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Contents SVM2608 VXI Technology, Inc Table of Contents Self Test Command Limitation of Warranty WarrantyCertification Restricted Rights LegendSteve Mauga, QA Manager EMCTerms and Symbols Service should only be performed by qualified personnelUse Proper Power Cord Use Proper Power SourceGround the Product Avoid Electric ShockOperating Conditions Improper UseVXI Technology Cleveland Instrument Division VXI Technology World HeadquartersVXI Technology Lake Stevens Instrument Division Technical SupportVXI Technology, Inc SVM2608 Preface Overview IntroductionScale Triggering Acquiring DataLinear Mode Delayed TriggerPre-Trigger Commands Fifo ModeCalibrations Test BusOption SVM2608 Block Diagram Physical Description SVM2608 Environmental SpecificationsGND CH1I CH3I Front Panel Interface WiringGND CH1I+ GND CH3I+ Exttrigin CH0I CH2IMtbf SVM2608 SpecificationsOption 1 SVM2608-01 VXI Technology, Inc SVM2608 Introduction Setting the Chassis Backplane Jumpers Calculating System Power and Cooling RequirementsRotary Switch Locations Setting the Base AddressExample Divide DecimalMSB LSB Module INSTALLATION/REMOVAL Switch to C and the front switch toFunction Offset Device Memory MapsReserved Register OffsetMS = Most Significant LS = Least Significant SVM2608 A32 Register MAP0x72 Command Register Channel 0x74 Databyte Ordering Determining the Register Address Accessing the Registers Description of RegistersSysfailctl INTLVL2 Force Trigger, Start Register 0x02 Read & WriteHSTRIGSRC2 EXT Trig SlopeTimeoutctl ReservedExternal Trigger Level 0x06 Read & Write 4WIREOHMS 2WIREOHMSLINEAR/FIFO ATTN-GAIN1-GAIN0Sample Rate 0x0C, 0x34, 0x5C, 0x84 Read & Write Sample Rate 0x0E, 0x36, 0x5E, 0x86 Read & WriteKHz Channels 0-3/5 MHz Channels 4-5 LPF Control This bit Sample Rate, High-Speed 0xAE, 0xD6 Read & Write Sample Rate, High-Speed 0xAC, 0xD4 Read & WriteTimeout 0x1C, 0x44, 0x6C, 0x94, 0xBC, 0xE4 Read & Write Fifo Data 0x24, 0x4C, 0x74, 0x9C, 0xC4, 0xEC Read Only Fifo Data 0x26, 0x4E, 0x76, 0x9E, 0xC6, 0xEE Read OnlyReserved Registers 0xF8 0xFC Trigger Delay = Measurement Commands Microprocessor CommandsCaptured Data Calculations Self Test Command Resistance Measurement Offset MethodResistance Measurement Dynamic Method Example Preset Setting Measurement CommandsSample Points Calibration CommandsSample Rate Trigger Event Forced TriggerPage Error Processing There are no errors in the queue Diagnostic Commands Changes become effective the next time the module powers up Examples Example 2 Setting Channel 2 to Acquire 200,000 SamplesExample 3 Setting Channel 2 to Pre-acquire 100,000 Samples Timeout Register = Timeout Base * 213 + Timeout Counter Timeout Counter = Timeout / Timeout Base ClockVXI Technology, Inc SVM2608 Programming Data Swapping Example Appendix aVXI Technology, Inc SVM2608 Appendix a Index