VXI SVM2608 Fifo Data 0x24, 0x4C, 0x74, 0x9C, 0xC4, 0xEC Read Only, Reserved Registers 0xF8 0xFC

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Command Register (0x22, 0x4A, 0x72, 0x9A, 0xC2, 0xEA) — Read and Write

 

 

Command Register - Writing to this register instructs the

 

 

microprocessor to perform the specified function. If this command

D15 – D0

CMD15 – 0

performs a calculation, the data is returned into the corresponding result

register.

 

 

For a detailed description of the commands, refer to the Microprocessor23

 

 

Commands section.

 

 

FIFO Data (0x24, 0x4C, 0x74, 0x9C, 0xC4, 0xEC) — Read Only

 

D15 – D0

FIFODATA31 – 16

FIFO Data - Two registers are provided for retrieving FIFO data. This

 

allows for 32-bit transfer. One sample of data per 16-bit register.

 

 

 

 

 

FIFO Data (0x26, 0x4E, 0x76, 0x9E, 0xC6, 0xEE) — Read Only

 

D15 – D0

FIFODATA15 – 0

FIFO Data - Two registers are provided for retrieving FIFO data. This

 

allows for 32-bit transfer. One sample of data per 16-bit register.

 

 

 

Results Register (0x28, 0x50, 0x78, 0xA0, 0xC8, 0xF0) — Read Only

 

 

Result Data - When a process data command is issued to the

D15 – D0

RESULT63 – 48

microprocessor, bits 63 through 48 of the 64-bit floating point result is

 

 

returned to this register. A status bit in the interrupt register is set.

Results Register (0x2A, 0x52, 0x7A, 0xA2, 0xCA, 0xF2) — Read Only

 

 

Result Data - When a process data command is issued to the

D15 – D0

RESULT47 – 32

microprocessor, bits 47 through 32 of the 64-bit floating point result is

 

 

returned to this register. A status bit in the interrupt register is set.

Results Register (0x2C, 0x54, 0x7C, 0xA4, 0xCB, 0xF4) — Read Only

D15 – D0

RESULT31 – 16

Result Data - When a process data command is issued to the

microprocessor, bits 31 through 16 of the 64-bit floating point result is

 

 

returned to this register. A status bit in the interrupt register is set.

Results Register (0x2E, 0x56, 0x7E, 0xA6, 0xCE, 0xF6) — Read Only

D15 – D0

RESULT15 – 0

Result Data - When a process data command is issued to the

microprocessor, bits 15 through 0 of the 64-bit floating point result is

 

 

returned to this register. A status bit in the interrupt register is set.

 

 

 

Reserved Registers (0xF8 – 0xFC)

 

D15 – D0

Unused

 

This is reserved for future use.

 

 

 

 

 

 

External Trigger Level - High-Speed Channels (0xFE) — Read & Write

 

 

 

 

High-Speed Input Trigger Source Slope – This bit sets the slope of the

 

 

HS_EXT_

 

input trigger for high-speed Channels 4 and 5.

 

D15

 

 

 

TRIG_SLOPE

 

0 = Positive

 

 

 

 

 

 

 

1 = Negative

 

 

 

 

Pon state = 0

 

D14 – D12

Unused

 

These bits are reserved for future use.

 

D11 – D 0

HS_EXT_TRIG 11 - 0

 

High-Speed External Trigger – Sets the level at which the high-speed

 

 

module triggers from an external source.

 

 

 

 

SVM2608 Programming

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Contents SVM2608 VXI Technology, Inc Table of Contents Self Test Command Restricted Rights Legend WarrantyLimitation of Warranty CertificationSteve Mauga, QA Manager EMCUse Proper Power Source Service should only be performed by qualified personnelTerms and Symbols Use Proper Power CordImproper Use Avoid Electric ShockGround the Product Operating ConditionsTechnical Support VXI Technology World HeadquartersVXI Technology Cleveland Instrument Division VXI Technology Lake Stevens Instrument DivisionVXI Technology, Inc SVM2608 Preface Overview IntroductionScale Triggering Acquiring DataLinear Mode Delayed TriggerPre-Trigger Test Bus Fifo ModeCommands CalibrationsOption SVM2608 Block Diagram Physical Description SVM2608 Environmental SpecificationsCH1I+ GND CH3I+ Exttrigin CH0I CH2I Front Panel Interface WiringGND CH1I CH3I GNDMtbf SVM2608 SpecificationsOption 1 SVM2608-01 VXI Technology, Inc SVM2608 Introduction Setting the Chassis Backplane Jumpers Calculating System Power and Cooling RequirementsRotary Switch Locations Setting the Base AddressExample Divide DecimalMSB LSB Module INSTALLATION/REMOVAL Switch to C and the front switch toRegister Offset Device Memory MapsFunction Offset ReservedMS = Most Significant LS = Least Significant SVM2608 A32 Register MAP0x72 Command Register Channel 0x74 Databyte Ordering Determining the Register Address Accessing the Registers Description of RegistersSysfailctl EXT Trig Slope Force Trigger, Start Register 0x02 Read & WriteINTLVL2 HSTRIGSRC2Timeoutctl ReservedExternal Trigger Level 0x06 Read & Write ATTN-GAIN1-GAIN0 2WIREOHMS4WIREOHMS LINEAR/FIFOSample Rate 0x0C, 0x34, 0x5C, 0x84 Read & Write Sample Rate 0x0E, 0x36, 0x5E, 0x86 Read & WriteKHz Channels 0-3/5 MHz Channels 4-5 LPF Control This bit Sample Rate, High-Speed 0xAE, 0xD6 Read & Write Sample Rate, High-Speed 0xAC, 0xD4 Read & WriteTimeout 0x1C, 0x44, 0x6C, 0x94, 0xBC, 0xE4 Read & Write Fifo Data 0x24, 0x4C, 0x74, 0x9C, 0xC4, 0xEC Read Only Fifo Data 0x26, 0x4E, 0x76, 0x9E, 0xC6, 0xEE Read OnlyReserved Registers 0xF8 0xFC Trigger Delay = Measurement Commands Microprocessor CommandsCaptured Data Calculations Self Test Command Resistance Measurement Offset MethodResistance Measurement Dynamic Method Example Preset Setting Measurement CommandsTrigger Event Forced Trigger Calibration CommandsSample Points Sample RatePage Error Processing There are no errors in the queue Diagnostic Commands Changes become effective the next time the module powers up Examples Example 2 Setting Channel 2 to Acquire 200,000 SamplesExample 3 Setting Channel 2 to Pre-acquire 100,000 Samples Timeout Register = Timeout Base * 213 + Timeout Counter Timeout Counter = Timeout / Timeout Base ClockVXI Technology, Inc SVM2608 Programming Data Swapping Example Appendix aVXI Technology, Inc SVM2608 Appendix a Index
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