VXI SVM2608 user manual Changes become effective the next time the module powers up

Page 50

VXI Technology, Inc.

FLASH Memory Programming Commands

The following commands can be used to change the content of the FLASH memory. The FLASH memory stores the board’s software (executed by the microprocessor) and firmware (what programs the two FPGAs on the board). To prevent accidental writings of the FLASH, a sequence of three commands is necessary to perform a write to it.

To change the microprocessor software, the new file that needs to be programmed into FLASH is uploaded at offset address 0x000000. Then, to change the software, the following three commands must be issued in this particular order. Issuing them in a different order will not produce any results:

0x5501, 0xAA01, 0x5501

After issuing each of the above commands, the user must wait until the command is executed before issuing the next one. When the second 0x5501 command is done, it means the new data has been moved into FLASH memory.

To change the firmware for the first FPGA (U1), the new file that needs to be programmed into FLASH is uploaded at offset address 0x000000. Then, the following three commands must be issued in this particular order. Issuing them in a different order will not produce any results:

0x5502, 0xAA02, 0x5502

After issuing each of the above commands, the user must wait until the command is executed before issuing the next one. When the second 0x5502 command is done, it means the new data has been moved into FLASH memory.

To change the firmware for the second FPGA (U20), the new file that needs to be programmed into FLASH is uploaded at offset address 0x000000. Then the following three commands must be issued in this particular order. Issuing them in a different order will not produce any results:

0x5503, 0xAA03, 0x5503

After issuing each of the above commands, the user must wait until the command is executed before issuing the next one. When the second 0x5503 command is done, it means the new data has been moved into FLASH memory.

To change the firmware for the third FPGA (U37), the new file that needs to be programmed into FLASH is uploaded at offset address 0x000000. Then the following three commands must be issued in this particular order. Issuing them in a different order will not produce any results:

0x5504, 0xAA04, 0x5504

After issuing each of the above commands, the user must wait until the command is executed before issuing the next one. When the second 0x5503 command is done, it means the new data has been moved into FLASH memory.

Changes become effective the next time the module powers up.

WARNING: ANY COMMANDS NOT LISTED HERE ARE RESERVED FOR FACTORY USE AND SHOULD NOT BE USED UNDER ANY CIRCUMSTANCES.

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SVM2608 Programming

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Contents SVM2608 VXI Technology, Inc Table of Contents Self Test Command Certification WarrantyLimitation of Warranty Restricted Rights LegendEMC Steve Mauga, QA ManagerUse Proper Power Cord Service should only be performed by qualified personnelTerms and Symbols Use Proper Power SourceOperating Conditions Avoid Electric ShockGround the Product Improper UseVXI Technology Lake Stevens Instrument Division VXI Technology World HeadquartersVXI Technology Cleveland Instrument Division Technical SupportVXI Technology, Inc SVM2608 Preface Introduction OverviewScale Acquiring Data TriggeringPre-Trigger Linear ModeDelayed Trigger Calibrations Fifo ModeCommands Test BusOption SVM2608 Block Diagram SVM2608 Environmental Specifications Physical DescriptionGND Front Panel Interface WiringGND CH1I CH3I CH1I+ GND CH3I+ Exttrigin CH0I CH2ISVM2608 Specifications MtbfOption 1 SVM2608-01 VXI Technology, Inc SVM2608 Introduction Calculating System Power and Cooling Requirements Setting the Chassis Backplane JumpersSetting the Base Address Rotary Switch LocationsMSB LSB ExampleDivide Decimal Switch to C and the front switch to Module INSTALLATION/REMOVALReserved Device Memory MapsFunction Offset Register OffsetSVM2608 A32 Register MAP MS = Most Significant LS = Least Significant0x72 Command Register Channel 0x74 Databyte Ordering Determining the Register Address Sysfailctl Accessing the RegistersDescription of Registers HSTRIGSRC2 Force Trigger, Start Register 0x02 Read & WriteINTLVL2 EXT Trig SlopeExternal Trigger Level 0x06 Read & Write TimeoutctlReserved LINEAR/FIFO 2WIREOHMS4WIREOHMS ATTN-GAIN1-GAIN0KHz Channels 0-3/5 MHz Channels 4-5 LPF Control This bit Sample Rate 0x0C, 0x34, 0x5C, 0x84 Read & WriteSample Rate 0x0E, 0x36, 0x5E, 0x86 Read & Write Sample Rate, High-Speed 0xAC, 0xD4 Read & Write Sample Rate, High-Speed 0xAE, 0xD6 Read & WriteTimeout 0x1C, 0x44, 0x6C, 0x94, 0xBC, 0xE4 Read & Write Reserved Registers 0xF8 0xFC Fifo Data 0x24, 0x4C, 0x74, 0x9C, 0xC4, 0xEC Read OnlyFifo Data 0x26, 0x4E, 0x76, 0x9E, 0xC6, 0xEE Read Only Trigger Delay = Microprocessor Commands Measurement CommandsCaptured Data Calculations Resistance Measurement Dynamic Method Self Test CommandResistance Measurement Offset Method Preset Setting Measurement Commands ExampleSample Rate Calibration CommandsSample Points Trigger Event Forced TriggerPage Error Processing There are no errors in the queue Diagnostic Commands Changes become effective the next time the module powers up Example 2 Setting Channel 2 to Acquire 200,000 Samples ExamplesExample 3 Setting Channel 2 to Pre-acquire 100,000 Samples Timeout Counter = Timeout / Timeout Base Clock Timeout Register = Timeout Base * 213 + Timeout CounterVXI Technology, Inc SVM2608 Programming Appendix a Data Swapping ExampleVXI Technology, Inc SVM2608 Appendix a Index
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