Atmel STK594 manual Port Connectors, Port E

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Using the STK594 Top Module

Figure 2-1.Connecting the STK594 to the STK500 Board

Note: Connecting the STK594 with the wrong orientation may damage the boards.

Note: Do not mount the STK594 at the same time an AVR is mounted on the STK500 board.

2.2PORT Connectors

2.2.1PORT E

Since the AT94K devices have additional ports not available on the STK500, these ports are located on the STK594 board. The STK594 ports have the same pinout and func- tionality as the ports on the STK500 board. Since Port A to Port D are already present on the STK500 board, they are not duplicated on the STK594.

Figure 2-2 shows the pinout for the I/O port headers Port E.

Figure 2-2.General I/O Ports

1 2

PE0 PE1

PE2 PE3

PE4 PE5

PE6 PE7

GND VTG

PORT E

Note: Port E is also present on the STK500, but only PE0 to PE2 (3 least significant bits) are accessible. To access all Port E bits the connector on the STK594 must be used.

2-2

FPSLIC STK594 User Guide

2819A–FPSLI–07/02

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Contents STK594 User Guide Page Table of Contents Technical Specifications Section Introduction STK594 Top Module for STK500Features Section Using the STK594 Top Module Adjusting Vtarget for the AT94K DevicesConnecting the STK594 to the STK500 Starter Kit Preparing the STK500 for Use with the STK594Port Connectors Port EJtag Second RS-232C Port Tosc SwitchUniversal Asynchronous Receiver Transmitter Uart Interrupts Two-Wire Serial Interface TwsiExternal Split Power Supply Support Xtal SwitchRequirements Section Installing System DesignerSystem Licensing System Designer InstallationConfiguration Programming System CPS Installation Configuring the System Designer License Installing System Designer Section Using System Designer DescriptionDesign Flow Creating a ProjectUsing System Designer Using System Designer Using System Designer Using System Designer File Assembling the Microcontroller Source CodeFpga Source AVR-FPGA InterfaceRoute Fpga I/O FPGA-AVR I/ODesign Constraints Place and RouteBitstream Generation Hardware Setup Programming and Design ExecutionUsing System Designer Running the Design Select Low under A2 Bit LevelSection Technical Specifications System UnitOperating Conditions ConnectionsTechnical Specifications Section Complete Schematics Complete Schematics CON52 GND AUXI0 AUXO0 AUXI1 Cclk VCC VDD Vout Schematics Complete Schematics Atmel Headquarters