Atmel STK594 manual Jtag

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Using the STK594 Top Module

2.3Programming the AT94K Devices

The FPSLIC configuration process involves configuring the FPGA, the AVR® program code and the FPSLIC data memory. This configuration requires a single bitstream that configures the FPGA, the embedded AVR Program SRAM and the FPSLIC Data SRAM. The combined bitstream is automatically generated by the Bitstream Generator, a System Designer software utility.

After a reset and the internal clearing of the configuration data, the FPSLIC device self- initiates configuration. The Master mode uses an internal oscillator to provide the Con- figuration Clock (CCLK) for clocking the external EEPROM (configurator), which contains the configuration data. After auto-configuration is complete, re-configuration can be initiated manually by the user, if needed.

Note: The AT94K devices also support Self-Programming. For more information on this topic, refer to the “Code-Self Modify” application note available on the Atmel web site.

Note: The AT94K devices also support Cache Logic® Configuration. For more infor- mation on this topic, refer to the “Cache Logic Configuration” application note available on the Atmel web site.

For more details on programming procedures, refer to Section 4.10.

2.4JTAG Connector The JTAG connector is intended for the AT94K devices that have a built-in JTAG inter- face. The pinout of the JTAG connector is shown in Figure 2-3 and is compliant with the pinout of the JTAG ICE available from Atmel. Connecting a JTAG ICE to this connector allows On-chip Debugging of the AT94K devices.

More information about the JTAG ICE and On-chip Debugging can be found in the AVR

JTAG ICE user guide, available on the Atmel web site.

Figure 2-3.JTAG Connector

1 2 TCK TDO TMS VTG

TDI

GND VTG RST N/C

GND

JTAG

Note: To determine if your AT94K device supports JTAG Debug, examine the date code. Any parts with a J after their date code support JTAG. Example, 4201J.

Figure 2-4 shows how to connect the JTAG ICE probe on the STK594 board.

Figure 2-4.Connecting JTAG ICE to the STK594

FPSLIC STK594 User Guide

2-3

2819A–FPSLI–07/02

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Contents STK594 User Guide Page Table of Contents Technical Specifications STK594 Top Module for STK500 Section IntroductionFeatures Adjusting Vtarget for the AT94K Devices Section Using the STK594 Top ModuleConnecting the STK594 to the STK500 Starter Kit Preparing the STK500 for Use with the STK594Port E Port ConnectorsJtag Tosc Switch Universal Asynchronous Receiver Transmitter UartSecond RS-232C Port Two-Wire Serial Interface Twsi ExternalInterrupts Xtal Switch Split Power Supply SupportSection Installing System Designer SystemRequirements System Designer Installation Configuration Programming System CPS InstallationLicensing Configuring the System Designer License Installing System Designer Description Section Using System DesignerCreating a Project Design FlowUsing System Designer Using System Designer Using System Designer Using System Designer Assembling the Microcontroller Source Code Fpga SourceFile Interface AVR-FPGAFpga I/O FPGA-AVR I/O RoutePlace and Route Design ConstraintsBitstream Generation Programming and Design Execution Hardware SetupUsing System Designer Select Low under A2 Bit Level Running the DesignSystem Unit Section Technical SpecificationsOperating Conditions ConnectionsTechnical Specifications Section Complete Schematics Complete Schematics CON52 GND AUXI0 AUXO0 AUXI1 Cclk VCC VDD Vout Schematics Complete Schematics Atmel Headquarters