Atmel STK594 manual Complete Schematics

Page 34

2819A–FPSLI–07/02

6-2

FPSLIC STK594 User Guide

5

D

C

B

A

5

 

4

 

 

3

 

2

1

 

 

 

SW1

 

 

 

 

 

 

TOSC1

1

 

 

 

 

 

TOSC1

2

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

TOSC2

4

 

 

 

 

 

TOSC2

5

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SW DPDT

 

R1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

200K

 

 

 

 

 

 

 

R2

 

 

 

 

 

 

 

10M

 

 

 

 

 

 

 

Y1

 

 

 

 

 

C1

 

32.768 kHz

C2

 

 

 

 

 

 

 

 

 

 

33 pF

 

 

27 pF

 

 

 

 

SW2

XT1

 

Y2

 

 

 

XTAL1

1

XT1

 

 

XTAL1

 

2

 

 

 

 

 

 

 

 

 

 

3

 

5

 

 

 

 

 

 

OUT

 

 

 

 

 

 

 

 

 

 

XTAL2

4

XT2

XT2

 

 

XTAL2

 

5

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

OSC8

 

 

 

 

 

 

 

 

 

 

 

SW DPDT

 

 

 

 

 

 

 

Title

 

ATSTK594 : Clock Circuitry

 

 

 

Size A

 

Document Number

CHW5472

 

 

 

 

 

 

 

Date:

 

Friday, April 26, 2002

 

 

Sheet 1of 6

 

 

 

 

 

 

4

3

 

 

2

 

1

Rev A

D

C

B

A

Complete Schematics

Image 34
Contents STK594 User Guide Page Table of Contents Technical Specifications Section Introduction STK594 Top Module for STK500Features Connecting the STK594 to the STK500 Starter Kit Section Using the STK594 Top ModuleAdjusting Vtarget for the AT94K Devices Preparing the STK500 for Use with the STK594Port Connectors Port EJtag Universal Asynchronous Receiver Transmitter Uart Tosc SwitchSecond RS-232C Port External Two-Wire Serial Interface TwsiInterrupts Split Power Supply Support Xtal SwitchSystem Section Installing System DesignerRequirements Configuration Programming System CPS Installation System Designer InstallationLicensing Configuring the System Designer License Installing System Designer Section Using System Designer DescriptionDesign Flow Creating a ProjectUsing System Designer Using System Designer Using System Designer Using System Designer Fpga Source Assembling the Microcontroller Source CodeFile AVR-FPGA InterfaceRoute Fpga I/O FPGA-AVR I/ODesign Constraints Place and RouteBitstream Generation Hardware Setup Programming and Design ExecutionUsing System Designer Running the Design Select Low under A2 Bit LevelOperating Conditions Section Technical SpecificationsSystem Unit ConnectionsTechnical Specifications Section Complete Schematics Complete Schematics CON52 GND AUXI0 AUXO0 AUXI1 Cclk VCC VDD Vout Schematics Complete Schematics Atmel Headquarters