Atmel STK594 manual Programming and Design Execution, Hardware Setup

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Using System Designer

Figure 4-17.Control Register Settings Dialog

5.Press OK to generate the combined bitstream file.

Note: It is possible to generate a bitstream for only the FPGA or AVR as you may only want to program that portion of the FPSLIC device. To include only the AVR HEX file, simply uncheck the Include FPGA Bitstream box. Programming only the FPGA portion can be done in a similar fashion.

4.10Programming and Design Execution

4.10.1Hardware Setup

The programming file generated by the Bitstream Generator is used to program the con- figuration memory. When the FPSLIC requests configuration data after a Reset or Power-On-Reset, the data is clocked out serially.

Before programming the configurator and verifying the tutorial design, a few prepara- tions need to be performed prior to its execution on hardware.

1.Connect the PC’s parallel port to the 25-pin connector of the ATDH2225 Pro- gramming Dongle.

2.Connect the 10-pin ISP header on the STK594 to the 10-pin ribbon cable of the ATDH2225. The ATDH2225 is keyed to assure proper orientation, see Figure 4- 18.

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FPSLIC STK594 User Guide

2819A–FPSLI–07/02

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Contents STK594 User Guide Page Table of Contents Technical Specifications Section Introduction STK594 Top Module for STK500Features Section Using the STK594 Top Module Adjusting Vtarget for the AT94K DevicesConnecting the STK594 to the STK500 Starter Kit Preparing the STK500 for Use with the STK594Port Connectors Port EJtag Universal Asynchronous Receiver Transmitter Uart Tosc SwitchSecond RS-232C Port External Two-Wire Serial Interface TwsiInterrupts Split Power Supply Support Xtal SwitchSystem Section Installing System DesignerRequirements Configuration Programming System CPS Installation System Designer InstallationLicensing Configuring the System Designer License Installing System Designer Section Using System Designer DescriptionDesign Flow Creating a ProjectUsing System Designer Using System Designer Using System Designer Using System Designer Fpga Source Assembling the Microcontroller Source CodeFile AVR-FPGA InterfaceRoute Fpga I/O FPGA-AVR I/ODesign Constraints Place and RouteBitstream Generation Hardware Setup Programming and Design ExecutionUsing System Designer Running the Design Select Low under A2 Bit LevelSection Technical Specifications System UnitOperating Conditions ConnectionsTechnical Specifications Section Complete Schematics Complete Schematics CON52 GND AUXI0 AUXO0 AUXI1 Cclk VCC VDD Vout Schematics Complete Schematics Atmel Headquarters