Xilinx XAPP169 manual National Semiconductor, Function Controller

Page 11

MP3 NG: A Next Generation Consumer Platform

R

National

Semiconductor

USBN9602 USB

Function

Controller

The USB interface in the design is based on a National Semiconductor USBN9602 controller. This device, packaged in a 28-pin SOIC package, supports full speed USB function controller operation and includes an integrated USB transceiver. It contains seven endpoint FIFOs, two of which are 64 bytes deep.

Figure 12 shows a block diagram of this device. The complete data sheet for the USBN9602 can be found at the following URL:

http://www.national.com/ds/US/USBN9602.pdf

CS

RD

WR

A0/ALE

D[7:0]/AD[7:0]

INTR

MODE[1:0]

 

 

 

 

 

 

 

 

 

RESET

 

 

Microcontroller Interface

 

 

 

Vcc

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

Endpoint/Control FIFOs

 

 

 

48 MHz

XIN

 

 

 

 

 

 

 

XOUT

 

Control

 

 

Status

 

Oscillator

 

 

 

 

 

 

Endpoint0

EP1 EP2

EP3 EP4

EP5 EP6

RX

 

Clock

CLKOUT

 

 

 

 

TX

 

Generator

 

 

 

 

 

SIE

 

 

 

 

 

 

 

 

 

Media Access Controller (MAC)

Clock

 

 

Recovery

 

 

 

 

 

 

 

 

 

Physical Layer Interface (PHY)

USB Event

 

 

 

 

 

 

 

 

 

 

 

Detect

 

 

 

 

 

 

 

 

 

V3.3

Transceiver

 

 

VReg

 

 

AGND

 

 

 

 

 

 

 

 

 

D+

D-

Upstream Port

 

 

 

 

Figure 12: USBN9602 Block Diagram

(Courtesy National Semiconductor)

The system interface for the USBN9602 is a simple 8-bit microprocessor bus that can be configured to operate in a multiplexed or non-multiplexed mode. The multiplexed mode is more attractive from a software perspective since it supports random access to the devices’ internal registers. This mode also reduces the number of interface pins required. For both of these reasons this was chosen for this application. Figure 13 shows read timing for the USBN9602 when operating in multiplexed mode.

XAPP169 (v1.0) November 24, 1999

www.xilinx.com

11

 

1-800-255-7778

 

Image 11
Contents MP3 Background MP3 NG a Next Generation Consumer PlatformSummary IntroductionMP3 NG a Next Generation Consumer Platform Solution OverviewMP3 Technology IDT RC32364 RISController MP3 NG System Block DiagramRC32364 Block Diagram RC32364 Read Timing Crystal CS4343 Stereo DAC CS4343 Block DiagramControl Port Timing Samsung Flash Memory KM29U64000T Block DiagramKM29U64000T Read Timing Micron Sdram MemoryMT48LC1M16A1 Block Diagram Function Controller National SemiconductorSoftware Architecture System ImplementationMP3 Decoder and Audio ISR UI ManagerCode Initialization Xilinx SpartanMemory Manager Block MappingIP Bus Controller Fpga Logic Block DiagramCPU Interface CPU Interface Block DiagramCpumasterclk LCD ControllerLCD Controller Interface Signal Summary LCD Controller Block DiagramMemory Interface Memory Interface Block DiagramFlash Controller Sdram Controller Interface Signal Summary Type DescriptionSdram Controller Performance Error HandlingIrda Controller Irda Controller Block DiagramAudio DAC Interface Audio DAC Interface Block DiagramTouch Screen Interface Audio DAC Interface Signal Summary Type DescriptionTotal 500 137 ConclusionSpartan Device Selection References Date Version # Revision 11/24/99 Initial release Revision History

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.