Xilinx XAPP169 manual UI Manager, MP3 Decoder and Audio ISR

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MP3 NG: A Next Generation Consumer Platform

R

UI

Manager

RTOS

 

 

 

MP3

 

 

 

 

 

 

 

 

 

 

Decoder

 

 

 

 

 

Audio

Memory

 

 

 

 

ISR

Manager

IRDA

USB

 

 

 

 

 

Stack

Stack

 

 

 

 

 

IR

USB

Touch

Screen

Audio

FLASH

MMU

BIOS

BIOS

BIOS

BIOS

BIOS

BIOS

BIOS

System

Hardware

Figure 14: System Software Architecture

The RTOS provides process scheduling and memory allocation functions. The RTOS could be any of the commercially available packages. Probably more of a factor than any technical issue is the licensing model for the product. Since this is a product that is targeted at the high-volume, cost sensitive, consumer market, an RTOS that is licensed on an up front fee basis with no unit royalties is the most attractive.

The various BIOS components will be discussed later in the sections that describe the hardware implementation for each interface. The key application modules are as follows:

UI Manager

The User Interface (UI) manager is responsible for handling interaction between the user and the system. This includes using the Screen BIOS to create the buttons and menus that the user sees, getting user input through the Touch BIOS and using this information to coordinate activities such as downloading and playing MP3 files. The UI manager would also spawn separate processes for value added features such as an appointment calendar, or a phone book, as needed.

MP3 Decoder and Audio ISR

The MP3 decoder runs as an independent process, controlled by the UI manager. When activated, it uses the FLASH BIOS to fetch MP3 file data, decompresses it and places the audio data in a queue. The audio Interrupt Service Routine (ISR) is activated by an interrupt from the Audio DAC block in the FPGA. When activated, it reads data from this queue and writes it to FIFOs in the Audio DAC block.

The key to getting optimal performance from the MP3 decoder on the RC32364 lies in taking advantage of the MAC instruction supported by the processor. The instruction is particularly valuable in the implementation of the Discrete Cosine Transform (DCT) for sub-band synthesis.

There are several sources for MP3 decoder code. A fixed point decoder (splay-0.81- fixpoint.tgz) that was developed for the Linux ARM project can be downloaded from the following URL:

ftp://ftp.netwinder.org/users/n/nico

XAPP169 (v1.0) November 24, 1999

www.xilinx.com

13

 

1-800-255-7778

 

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Contents Summary MP3 NG a Next Generation Consumer PlatformIntroduction MP3 BackgroundMP3 Technology Solution OverviewMP3 NG a Next Generation Consumer Platform IDT RC32364 RISController MP3 NG System Block DiagramRC32364 Block Diagram RC32364 Read Timing Crystal CS4343 Stereo DAC CS4343 Block DiagramControl Port Timing Samsung Flash Memory KM29U64000T Block DiagramKM29U64000T Read Timing Micron Sdram MemoryMT48LC1M16A1 Block Diagram Function Controller National SemiconductorSoftware Architecture System ImplementationMP3 Decoder and Audio ISR UI ManagerMemory Manager Xilinx SpartanBlock Mapping Code InitializationIP Bus Controller Fpga Logic Block DiagramCPU Interface CPU Interface Block DiagramCpumasterclk LCD ControllerLCD Controller Interface Signal Summary LCD Controller Block DiagramMemory Interface Memory Interface Block DiagramSdram Controller Sdram Controller Interface Signal Summary Type DescriptionFlash Controller Performance Error HandlingIrda Controller Irda Controller Block DiagramAudio DAC Interface Audio DAC Interface Block DiagramTouch Screen Interface Audio DAC Interface Signal Summary Type DescriptionSpartan Device Selection ConclusionTotal 500 137 References Date Version # Revision 11/24/99 Initial release Revision History

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.