Xilinx XAPP169 manual LCD Controller, Cpumasterclk

Page 17

MP3 NG: A Next Generation Consumer Platform

Table 1: CPU Interface Signal Summary

R

Signal

Type

Description

 

 

 

CPU_MASTERCLK

Output

All bus timing is relative to this clock. The CPU core frequency is derived by

 

 

multiplying this clock.

 

 

 

CPU_AD[31:0]

I/O

High-order multiplexed address and data bits.

 

 

 

CPU_ADDR[3:2]

Input

Non-multiplexed address lines. These serve as the word within block address for

 

 

cache refills (Addr[3:2]).

 

 

 

CPU_BE_N[3:0]

Input

Indicates which byte lanes are expected to participate in the transfer.

 

 

 

CPU_ALE

Input

Address latch enable.

 

 

 

CPU_CIP_N

Input

Denotes that a cycle is in progress. Asserted in the address phase and is asserted

 

 

until the ACK* for the last data is sampled.

 

 

 

CPU_RD_N

Input

This active Low signal indicates that the current transaction is a read.

 

 

 

CPU_WR_N

Input

This active Low signal indicates that the current cycle transaction is a write.

 

 

 

CPU_BUSGNT_N

Output

During the power-on reset (Cold Reset), BusGnt* is an input and is used to load

 

 

ModeBit(5).

 

 

 

CPU_ACK_N

Output

On read transactions, this signals the RC32364 that the memory system has placed

 

 

valid data on the A/D bus, and that the processor may move the data into the on-

 

 

chip Read Buffer. On a write transaction, this signals to the RC32364 that the

 

 

memory system has accepted the data on the A/D bus.

 

 

 

CPU_RESET_N

Output

This active Low signal is used for both power-on and warm reset.

 

 

 

CPU_COLDRESET_N

Output

This active Low signal is used for power-on reset.

 

 

 

CPU_INT_N[3:0]

Output

Active Low interrupt signals to the CPU. During power-on, Int*(3:0)serves as

 

 

ModeBit(9:6).

 

 

 

US_CS_N

Output

USB controller chip select.

 

 

 

US_RD_N

Output

USB controller read strobe.

 

 

 

US_WR_N

Output

USB controller write strobe.

 

 

 

There is no direct software support required for this block, but the USB interface itself requires considerable software for operation. This software consists of the USB protocol stack, which includes a USB interrupt service routine. The USB stack itself consists of two parts. The first of these is the software required for participating in the USB protocol and the plug and play. The second part is the application specific code required to transfers MP3 files from the host system to the player.

LCD Controller

The LCD Controller is responsible for refreshing the screen with an image stored in the SDRAM. In general its operation is similar to that of a CRT display controller. Unlike most display controllers, the display format generated by the LCD controllers is not programmable by the CPU. The raster format is fixed at 128 x 128 pixels and the display timing is fixed as well. This makes sense in an embedded system such as this where the display is integrated into the unit. Although the display format cannot be changed in the system, loading different FPGA configurations into the FLASH when the unit is manufactured can accommodate different displays. Figure 17 shows the block diagram of the LCD Controller.

XAPP169 (v1.0) November 24, 1999

www.xilinx.com

17

 

1-800-255-7778

 

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Contents Summary MP3 NG a Next Generation Consumer PlatformIntroduction MP3 BackgroundMP3 NG a Next Generation Consumer Platform Solution OverviewMP3 Technology IDT RC32364 RISController MP3 NG System Block DiagramRC32364 Block Diagram RC32364 Read Timing Crystal CS4343 Stereo DAC CS4343 Block DiagramControl Port Timing Samsung Flash Memory KM29U64000T Block DiagramKM29U64000T Read Timing Micron Sdram MemoryMT48LC1M16A1 Block Diagram Function Controller National SemiconductorSoftware Architecture System ImplementationMP3 Decoder and Audio ISR UI ManagerMemory Manager Xilinx SpartanBlock Mapping Code InitializationIP Bus Controller Fpga Logic Block DiagramCPU Interface CPU Interface Block DiagramCpumasterclk LCD ControllerLCD Controller Interface Signal Summary LCD Controller Block DiagramMemory Interface Memory Interface Block DiagramFlash Controller Sdram Controller Interface Signal Summary Type DescriptionSdram Controller Performance Error HandlingIrda Controller Irda Controller Block DiagramAudio DAC Interface Audio DAC Interface Block DiagramTouch Screen Interface Audio DAC Interface Signal Summary Type DescriptionTotal 500 137 ConclusionSpartan Device Selection References Date Version # Revision 11/24/99 Initial release Revision History

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.
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