Xilinx XAPP169 Solution Overview, MP3 Technology, MP3 NG a Next Generation Consumer Platform

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MP3 NG: A Next Generation Consumer Platform

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Solution Overview

MP3 Technology

MP3 refers to the MPEG Layer 3 audio compression scheme that was defined as part of the International Standards Organization (ISO) Moving Picture Experts Group (MPEG) audio/video coding standard. MPEG-I defined three encoding schemes, referred to as Layer 1, Layer 2, and Layer 3. Each of these schemes uses increasing sophisticated encoding techniques and gives correspondingly better audio quality at a given bit rate. The three layers are hierarchical, in that a Layer 3 decoder can decode Layer 1, 2, and 3 bitstreams; a Layer 2 decoder can decode Layer 2, and 1 bitstreams; and a Layer 1 decoder can only decode Layer 1 bitstreams. Each of the layers support decoding audio sampled at 48, 44.1, or 32 kHz. MPEG 2 uses the same family of codecs but extends it by adding support for 24, 22.05, or 16 kHz sampling rates as well as more audio channels for surround sound and multilingual applications.

All Layers use the same basic structure. The coding scheme can be described as "perceptual noise shaping" or "perceptual subband / transform coding". The encoder analyzes the spectral components of the audio signal by calculating a filterbank (transform) and applies a psycho- acoustic model to estimate the just noticeable noise-level. In its quantization and coding stage, the encoder tries to allocate the available number of data bits in a way to meet both the bitrate and masking requirements. In plain English, the algorithm exploits the fact that loud sounds mask out the listener’s ability to perceive quieter sounds in the same frequency range. The encoder uses this property to remove information from the signal that would not be heard anyway.

Like all of the MPEG compression technologies, the algorithms are designed so that the decoder is much less complex. Its only task is to synthesize an audio signal out of the coded spectral components. All Layers use the same analysis filter bank (polyphase with 32 sub- bands). Layer 3 adds a MDCT transform to increase the frequency resolution.

All layers use the same header information in their bitstream to support the hierarchical structure of the standard.

A key design objective for this application was the creation of a solution with the lowest possible cost, while at the same time providing support for value added features. These features include the ability to store contact information and record memos and other functions commonly found in Personal Digital Assistants (PDAs).

Figure 1 gives an overview of the design. The key features of which are:

•128 x 128 pixel graphical touch screen.

•USB interface for download music and network connectivity.

•IRDA compliant infrared interface for exchanging data with other units.

•32 MB of on board FLASH storage.

•CompactFlash interface for storage expansion using CompactFlash cards or MicroDrive hard drives.

All of this is driven by a high-performance IDT RC32364 32-bit RISC processor and interfaced using a next generation Spartan-II FPGA. Before the functions implemented in the Spartan device and the software function running on the RC32364 are examined, the following gives an overview of the Application Specific Standard Products (ASSPs) that are included in the design.

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www.xilinx.com

XAPP169 (v1.0) November 24, 1999

 

1-800-255-7778

 

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Contents Introduction MP3 NG a Next Generation Consumer PlatformSummary MP3 BackgroundMP3 NG a Next Generation Consumer Platform Solution OverviewMP3 Technology MP3 NG System Block Diagram IDT RC32364 RISControllerRC32364 Block Diagram RC32364 Read Timing CS4343 Block Diagram Crystal CS4343 Stereo DACControl Port Timing KM29U64000T Block Diagram Samsung Flash MemoryMicron Sdram Memory KM29U64000T Read TimingMT48LC1M16A1 Block Diagram National Semiconductor Function ControllerSystem Implementation Software ArchitectureUI Manager MP3 Decoder and Audio ISRBlock Mapping Xilinx SpartanMemory Manager Code InitializationFpga Logic Block Diagram IP Bus ControllerCPU Interface Block Diagram CPU InterfaceLCD Controller CpumasterclkLCD Controller Block Diagram LCD Controller Interface Signal SummaryMemory Interface Block Diagram Memory InterfaceFlash Controller Sdram Controller Interface Signal Summary Type DescriptionSdram Controller Error Handling PerformanceIrda Controller Block Diagram Irda ControllerAudio DAC Interface Block Diagram Audio DAC InterfaceAudio DAC Interface Signal Summary Type Description Touch Screen InterfaceTotal 500 137 ConclusionSpartan Device Selection References Revision History Date Version # Revision 11/24/99 Initial release

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.
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