Xilinx XAPP169 manual Sdram Controller, Flash Controller

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MP3 NG: A Next Generation Consumer Platform

R

SDRAM Controller

The SDRAM controller design (Figure 19) is based on the design developed by Xilinx in application note XAPP134: Virtex Synthesizable High Performance SDRAM Controller. The changes made in the original design are to adapt to the differences in the host interface. In the original design the host interface is a multiplexed address data bus. In this application the IP bus is non-multiplexed. Another difference is that the original design supported a 32-bit wide memory configuration with two MT48LC1M16 memory devices. In the design a 16-bit wide memory datapath and a single MT48LC1M16 is used.

SYS_CLK

SDRAM_SEL_N

ACK_N

WR_IN_N[3:0]

RD_IN_N

 

sdrm_t.v from XAPP 134

State

State

Machine

Machine

 

Refresh

 

Counter

 

32

SD_BA

SA_CS

SD_CLK

SD_CKE

SD_RAS

SD_CAS

SD_WE SD_DQML

Figure 19: Figure 19 SDRAM Controller Block Diagram

The estimated FPGA device resources used to implement this block include an estimated 100 CLBs, two DLLs, two global clock buffers and the nine I/O pads listed in Table 3. There is no software support required for this block.

Table 3: SDRAM Controller Interface Signal Summary

Signal

Type

Description

 

 

 

SD_BA

Output

Bank address

 

 

 

SD_CS

Output

Chip select

 

 

 

SD_CLK

Output

Transfer clock

 

 

 

SD_CKE

Output

Clock enable

 

 

 

SD_RAS

Output

Row address strobe

 

 

 

SD_CAS

Output

Column address strobe

 

 

 

SD_WE

Output

Write enable

 

 

 

SD_DQML

Output

Lower byte data mask

 

 

 

SD_DQMH

Output

Higher byte data mask

 

 

 

FLASH Controller

The largest cost associated with this design is the large amount of FLASH memory, 32 MB or more, that is required for storing MP3 audio files. In order to leverage this cost it is desirable to use this memory for all non-volatile storage requirements within the system. This includes code storage for the CPU as well as storage of the MP3 audio stream. (See Figure 20.)

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www.xilinx.com

XAPP169 (v1.0) November 24, 1999

 

1-800-255-7778

 

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Contents MP3 NG a Next Generation Consumer Platform SummaryIntroduction MP3 BackgroundMP3 NG a Next Generation Consumer Platform Solution OverviewMP3 Technology MP3 NG System Block Diagram IDT RC32364 RISControllerRC32364 Block Diagram RC32364 Read Timing CS4343 Block Diagram Crystal CS4343 Stereo DACControl Port Timing KM29U64000T Block Diagram Samsung Flash MemoryMicron Sdram Memory KM29U64000T Read TimingMT48LC1M16A1 Block Diagram National Semiconductor Function ControllerSystem Implementation Software ArchitectureUI Manager MP3 Decoder and Audio ISRXilinx Spartan Memory ManagerBlock Mapping Code InitializationFpga Logic Block Diagram IP Bus ControllerCPU Interface Block Diagram CPU InterfaceLCD Controller CpumasterclkLCD Controller Block Diagram LCD Controller Interface Signal SummaryMemory Interface Block Diagram Memory InterfaceFlash Controller Sdram Controller Interface Signal Summary Type DescriptionSdram Controller Error Handling PerformanceIrda Controller Block Diagram Irda ControllerAudio DAC Interface Block Diagram Audio DAC InterfaceAudio DAC Interface Signal Summary Type Description Touch Screen InterfaceTotal 500 137 ConclusionSpartan Device Selection References Revision History Date Version # Revision 11/24/99 Initial release

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.
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