Xilinx XAPP169 manual LCD Controller Block Diagram, LCD Controller Interface Signal Summary

Page 18

MP3 NG: A Next Generation Consumer Platform

 

 

 

 

Shift

 

 

FIFO

Register

 

DIN[31:0]

32

 

32

 

4

D

Q

D

Q

DI_D[3:0]

 

 

 

Enable

 

 

Wr

Rd

Load

 

 

 

 

State

 

 

 

 

Machine

 

 

SYS_CLK

 

 

 

 

 

BREQ_N

 

 

 

 

DI_XSCL

 

 

 

 

DI_LP

BGNT_N

 

 

 

 

 

 

 

 

DI_FR

RD_N

 

 

 

 

 

 

 

 

DI_YD

ACK_N

 

 

 

 

 

 

 

 

DI_YSCL

 

 

 

 

 

 

Address

 

 

 

 

Counter

 

 

 

AOUT[10:2]

9

9

9

 

 

Q

D

 

 

 

 

Enable

 

 

 

 

 

Load

 

 

 

AOUT[31:11]

21

 

 

Base

 

 

 

 

Address

 

 

 

 

Figure 17: LCD Controller Block Diagram

R

The LCD Controller is an IP bus master and fetches data for screen refresh independently of CPU activities. The display data that is fetched is loaded into a FIFO using a block transfer across the IP bus. The shift register loads display data from the FIFO and shifts it out as a 4-bit wide data stream at 16 MHz the maximum shift rate supported by the display drivers.

In order to prevent disruption of the display image, the FIFO must have a new data word available for the shift register every time it empties. This occurs every 500 ns (1 / [16 MHz / 8]). Since there is a significant amount of overhead associated with each non-sequential access to the SDRAM memory, fetches are made from it using multi-word bursts. The size of these bursts is a compromise between different factors. Longer bursts are more efficient since the SDRAM access overhead is amortized over a larger number of data words. Smaller bursts reduce the size of the FIFO and also reduce bus latency by reducing the time that the LCD controller ties up the IP bus. For this application a 2-word burst was chosen. The result is a 3-word deep FIFO and display buffer fetches every 1 ∝s.

The FPGA device resources used to implement this block include an estimated 58 CLBs and the nine I/O pads listed in Table 2.

 

Table 2: LCD Controller Interface Signal Summary

 

 

 

 

 

 

 

Signal

Type

Description

 

 

 

 

 

 

 

DI_XD[3:0]

Output

X driver data

 

 

 

 

 

 

 

DI_XSCL

Output

X driver data shift clock

 

 

 

 

 

 

 

DI_LP

Output

Latch pulse

 

 

 

 

 

 

 

DI_FR

Output

Frame signal

 

 

 

 

 

 

 

DI_YD

Output

Y driver scan start pulse

 

 

 

 

 

 

 

DI_YSCL

Output

Y driver shift clock

 

 

 

 

 

 

 

 

 

 

 

18

 

 

www.xilinx.com

XAPP169 (v1.0) November 24, 1999

 

 

 

1-800-255-7778

 

Page 17 Page 19
Image 18
Page 17 Page 19
Contents Introduction MP3 NG a Next Generation Consumer PlatformSummary MP3 BackgroundSolution Overview MP3 TechnologyMP3 NG a Next Generation Consumer Platform MP3 NG System Block Diagram IDT RC32364 RISControllerRC32364 Block Diagram RC32364 Read Timing CS4343 Block Diagram Crystal CS4343 Stereo DACControl Port Timing KM29U64000T Block Diagram Samsung Flash MemoryMicron Sdram Memory KM29U64000T Read TimingMT48LC1M16A1 Block Diagram National Semiconductor Function ControllerSystem Implementation Software ArchitectureUI Manager MP3 Decoder and Audio ISRBlock Mapping Xilinx SpartanMemory Manager Code InitializationFpga Logic Block Diagram IP Bus ControllerCPU Interface Block Diagram CPU InterfaceLCD Controller CpumasterclkLCD Controller Block Diagram LCD Controller Interface Signal SummaryMemory Interface Block Diagram Memory InterfaceSdram Controller Interface Signal Summary Type Description Sdram ControllerFlash Controller Error Handling PerformanceIrda Controller Block Diagram Irda ControllerAudio DAC Interface Block Diagram Audio DAC InterfaceAudio DAC Interface Signal Summary Type Description Touch Screen InterfaceConclusion Spartan Device SelectionTotal 500 137 References Revision History Date Version # Revision 11/24/99 Initial release

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.
Top Page Image Contents