Xilinx XAPP169 manual RC32364 Block Diagram

Page 4

MP3 NG: A Next Generation Consumer Platform

R

The variable page size lets each mapping independently represent memory regions that can range from 4 KB to 16 MB. This feature lets the system designer adjust the address mapping granularity for different memory regions.

Locking TLB entries excludes entries from being recommended for replacement when there is an address miss. This lets the system designer have mappings for critical regions of code and or data locked into the TLB for predictable real time performance.

RISCore32300TM

MMU

RISCore4000 Compatible

 

Extended MIPS 32

w/

System Control

 

Integer CPU Core

TLB

Coprocessor (CPO)

Enhanced JTAG (ICE

8kB

I-Cache,

 

2kB D-Cache, 2-set,

2-set,

lockable

 

Interface)

 

lockable, write-back/write-through

 

 

 

 

 

 

 

Clock

 

RISCore32300 Internal Bus Interface

 

Generation

 

 

 

 

Unit

 

 

 

 

RC32364 Bus Interface Unit

Figure 2: RC32364 Block Diagram

(Courtesy IDT)

Virtual Address with 1M (220) 4-Kbyte pages

39

32 31 29 28

20 bits = 1M

12 11

0

ASID

VPN

Offset

8

 

 

 

20

12

 

 

Bits 31, 30 and 29 of the virtual address select user, super- visor, or kernel address spaces.

 

 

 

 

 

 

 

 

 

 

Virtual-to-physical-

 

 

Offset

passed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

translation in TLB

 

 

unchanged

 

to

 

 

 

 

 

 

TLB

32-bit Physical Address

 

 

physical memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

PFN

 

Offset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Virtual-to-

 

 

Offset

pa ssed

 

 

 

 

 

 

 

 

 

physical transla-

 

 

 

 

 

 

 

 

 

 

 

 

unchanged to

physical

 

 

 

TLB

 

 

 

 

tion in TLB

 

 

 

 

 

 

 

 

 

 

 

 

memory.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

39

32

31

29 28

24

23

0

ASID

VPN

Offset

8

8

24

8 bits = 256 pages

Virtual Address with 256 (28)16-Mbyte pages

Figure 3: RC32364 Address Translation

(Courtesy IDT)

4

www.xilinx.com

XAPP169 (v1.0) November 24, 1999

 

1-800-255-7778

 

Image 4
Contents MP3 NG a Next Generation Consumer Platform SummaryIntroduction MP3 BackgroundMP3 Technology Solution OverviewMP3 NG a Next Generation Consumer Platform MP3 NG System Block Diagram IDT RC32364 RISControllerRC32364 Block Diagram RC32364 Read Timing CS4343 Block Diagram Crystal CS4343 Stereo DACControl Port Timing KM29U64000T Block Diagram Samsung Flash MemoryMicron Sdram Memory KM29U64000T Read TimingMT48LC1M16A1 Block Diagram National Semiconductor Function ControllerSystem Implementation Software ArchitectureUI Manager MP3 Decoder and Audio ISRXilinx Spartan Memory ManagerBlock Mapping Code InitializationFpga Logic Block Diagram IP Bus ControllerCPU Interface Block Diagram CPU InterfaceLCD Controller CpumasterclkLCD Controller Block Diagram LCD Controller Interface Signal SummaryMemory Interface Block Diagram Memory InterfaceSdram Controller Sdram Controller Interface Signal Summary Type DescriptionFlash Controller Error Handling PerformanceIrda Controller Block Diagram Irda ControllerAudio DAC Interface Block Diagram Audio DAC InterfaceAudio DAC Interface Signal Summary Type Description Touch Screen InterfaceSpartan Device Selection ConclusionTotal 500 137 References Revision History Date Version # Revision 11/24/99 Initial release

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.