Xilinx XAPP169 manual CPU Interface Block Diagram

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MP3 NG: A Next Generation Consumer Platform

R

CPU Interface

The CPU Interface block performs three functions: protocol conversion, CPU initialization and address de-multiplexing. Figure 16 shows a block diagram of this block.

 

CPU

 

 

 

Initialization

 

 

CPU_COLDRESET_N

 

 

IR_INT_N

CPU_RESET_N

 

 

DAC_INT_N

CPU_BUSGNT_N

 

 

 

CPU_INT_N[3:0]

 

 

SYS_CLK

 

 

 

DIN[31:0]

CPU_AD[31:0]

 

 

 

 

 

 

DOUT[31:0]

 

Latch

 

 

28

 

28

 

D

Q

AOUT[31:4]

CPU_ALE

Enable

 

 

 

 

2

CPU_ADDR[3:2]

 

 

AOUT[3:2]

CPU_MASTERCLK

 

 

 

 

Bus State

 

 

 

Machine

 

 

CPU_CIP_N

 

 

SYS_CLK

CPU_BE_N[3:0]

 

 

 

CPU_RD_N

 

 

RD_OUT_N

CPU_WR_N

 

 

 

 

WR_OUT_N[3:0]

CPU_ACK_N

 

 

 

 

ACK_IN

 

 

 

USB_CS_N

 

 

REQ_OUT

 

 

GNT_IN

USB_RD_N

 

 

 

 

 

USB_WR_N

 

 

 

Figure 16: CPU Interface Block Diagram

The CPU initialization block generates the required timing for the reset signals and drives configuration information onto bus grant and the interrupts. This configuration information configures the boot PROM width and enables the CPU timer. After initialization is complete the block drives the IRDA and audio DAC interrupts out onto the CPU interrupt signals.

The bus state machine converts the signaling on the CPU bus into the format used on the local IP bus, or if the transaction is to the USB interface, the signaling accepted by the USBN9602.

The FPGA device resources used to implement this block include an estimated 46 CLBs and the 54 I/O pads listed in Table 1.

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www.xilinx.com

XAPP169 (v1.0) November 24, 1999

1-800-255-7778

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Contents MP3 NG a Next Generation Consumer Platform SummaryIntroduction MP3 BackgroundMP3 Technology Solution OverviewMP3 NG a Next Generation Consumer Platform MP3 NG System Block Diagram IDT RC32364 RISControllerRC32364 Block Diagram RC32364 Read Timing CS4343 Block Diagram Crystal CS4343 Stereo DACControl Port Timing KM29U64000T Block Diagram Samsung Flash MemoryMicron Sdram Memory KM29U64000T Read TimingMT48LC1M16A1 Block Diagram National Semiconductor Function ControllerSystem Implementation Software ArchitectureUI Manager MP3 Decoder and Audio ISRXilinx Spartan Memory ManagerBlock Mapping Code InitializationFpga Logic Block Diagram IP Bus ControllerCPU Interface Block Diagram CPU InterfaceLCD Controller CpumasterclkLCD Controller Block Diagram LCD Controller Interface Signal SummaryMemory Interface Block Diagram Memory InterfaceSdram Controller Sdram Controller Interface Signal Summary Type DescriptionFlash Controller Error Handling PerformanceIrda Controller Block Diagram Irda ControllerAudio DAC Interface Block Diagram Audio DAC InterfaceAudio DAC Interface Signal Summary Type Description Touch Screen InterfaceSpartan Device Selection ConclusionTotal 500 137 References Revision History Date Version # Revision 11/24/99 Initial release

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.
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