Xilinx XAPP169 manual Samsung Flash Memory, KM29U64000T Block Diagram

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MP3 NG: A Next Generation Consumer Platform

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Samsung FLASH Memory

The FLASH memory chosen for this design is the KM29U64000T 8M x 8 device from Samsung Semiconductor. This device is based on NAND FLASH technology and is popular in MP3 player applications due to its high density and low cost per bit.

Figure 8 shows the block diagram for this device. The complete data sheet for the KM29U64000T can be found at the following URL:

http://www.usa.samsungsemi.com/products/prodspec/flash/km29u64000(i)t.pdf

 

 

Y-Gating

 

 

 

A9 - A22

X-Buffers

2nd half Page Register & S/A

 

 

 

 

 

 

Latches

 

 

 

 

 

 

 

 

 

 

& Decoders

64M + 2M Bit

 

 

 

 

 

 

 

 

 

Y-Buffers

NAND Flash

 

 

 

A 0 - A7

ARRAY

 

 

 

Latches

 

 

 

 

 

 

 

 

 

 

& Decoders

(512 + 16)Byte x 16384

 

 

 

 

 

 

 

 

 

 

1st half Page Register & S/A

 

 

 

 

A8

Y-Gating

 

 

 

Command

 

 

 

 

 

 

 

 

 

 

Command

 

 

 

 

 

Register

I/O Buffers & Latches

 

 

VCCQ

 

 

 

 

 

 

 

 

 

VSS

CE

Control Logic

 

 

 

 

RE

& High Voltage

 

Output

I/0 0

WE

Generator

Global Buffers

 

 

Driver

I/0 7

 

 

 

 

 

 

 

 

 

 

CLE ALE WP

 

 

 

 

Figure 8: KM29U64000T Block Diagram

(Courtesy Samsung Semiconductor)

Unfortunately this device also has two characteristics that present significant system level design challenges. The first of these is the narrow, highly multiplexed interface that is used to access the device. The KM29U64000T interfaces to the system through an 8-bit wide port that is used for both address and data. Figure 9 illustrates the read timing for this device.

The second and most challenging issue relates to data integrity, which is an issue common to most devices using NAND technology. There are two aspects to this, the first of which is the fact that devices when shipped may have memory blocks that may not be used due to data errors. The data sheet for the device has a parameter called NVB that is the number valid blocks that the device contains. The value of NVB varies from device to device and is specified to have a minimum of 1014, a maximum of 1024, and typically 1020. While the first block is guaranteed to be good, bad blocks can occur at any other location within the memory array. Invalid blocks are marked at the factory by storing a "0" value at location "0" in either the first or second block of the page. The system level impact of this is that it must keep track of which blocks are good within the device and that this results in a non-contiguous memory map.

The second issue is that while the device is guaranteed to provide at least the minimum number of valid blocks over its operational lifetime these devices may experience failures in additional blocks throughout their life. In order to ensure system integrity some form of error detection and correction must be implemented.

The discussion of the FLASH memory interface will discuss how these issues were addressed in this design.

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www.xilinx.com

XAPP169 (v1.0) November 24, 1999

 

1-800-255-7778

 

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Contents MP3 NG a Next Generation Consumer Platform SummaryIntroduction MP3 BackgroundMP3 NG a Next Generation Consumer Platform Solution OverviewMP3 Technology MP3 NG System Block Diagram IDT RC32364 RISControllerRC32364 Block Diagram RC32364 Read Timing CS4343 Block Diagram Crystal CS4343 Stereo DACControl Port Timing KM29U64000T Block Diagram Samsung Flash MemoryMicron Sdram Memory KM29U64000T Read TimingMT48LC1M16A1 Block Diagram National Semiconductor Function ControllerSystem Implementation Software ArchitectureUI Manager MP3 Decoder and Audio ISRXilinx Spartan Memory ManagerBlock Mapping Code InitializationFpga Logic Block Diagram IP Bus ControllerCPU Interface Block Diagram CPU InterfaceLCD Controller CpumasterclkLCD Controller Block Diagram LCD Controller Interface Signal SummaryMemory Interface Block Diagram Memory InterfaceFlash Controller Sdram Controller Interface Signal Summary Type DescriptionSdram Controller Error Handling PerformanceIrda Controller Block Diagram Irda ControllerAudio DAC Interface Block Diagram Audio DAC InterfaceAudio DAC Interface Signal Summary Type Description Touch Screen InterfaceTotal 500 137 ConclusionSpartan Device Selection References Revision History Date Version # Revision 11/24/99 Initial release

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.