Xilinx XAPP169 manual Xilinx Spartan, Memory Manager, Block Mapping, Code Initialization

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MP3 NG: A Next Generation Consumer Platform

The reference code that was developed for the standard is available from the Fraunhofer

Institute at the following URL:

http://www.iis.fhg.de/amm/techinf/layer3/index.html

A commercial decoder is available from Xaudio. Information on the Xaudio product line is available from:

http://www.xaudio.com

Memory Manager

R

Xilinx

Spartan- II

FPGA

The Memory Manager handles the tasks required to mask NAND FLASH issues from the other software in the system. Specifically these tasks are block mapping and code initialization.

Block Mapping

This involves maintaining a table of valid FLASH blocks and configuring the MMU to map them into a linear address space. For the FLASH memory space the TLB entries are set to the same 8 KB size to match the block size of the FLASH itself, and the entries are not locked in the TLB. A single TLB entry is used to map the SDRAM memory space. This entry is configured to map a 4 MB memory space and is locked in the TLB.

In the event that an error is detected in a valid block, this code is also responsible for copying the data to an unused block and marking the block in which the error was detected as bad.

Code Initialization

This function copies the code image from FLASH to RAM at boot time. This routine must also perform error detection on the image as it is copied. If an error is detected, error correction must be performed and the block mapping code informed.

Figure 15 shows the architecture implemented in the Spartan-II device for this application. It consists of eight major functional blocks:

•IP Bus Controller

•CPU Interface

•LCD Controller

•Memory Datapath

•SDRAM Controller

•FLASH Controller

•CompactFlash Controller

•IRDA Controller

•DAC Interface

•Touch Screen Interface

These blocks are interconnected by a simple non-multiplexed, multi-master, address data bus that is referred to as the IP bus. While the IP bus may appear to be a bus to the function blocks, it is not a bus at all but instead uses multiplexers for gating data into the internal datapaths. This approach eliminates the need for 3-state drivers within the design. In this implementation the bus has two masters; the CPU Interface and the LCD Controller. Figure 15 shows a top level block diagram of the FPGA.

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www.xilinx.com

XAPP169 (v1.0) November 24, 1999

 

1-800-255-7778

 

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Contents Introduction MP3 NG a Next Generation Consumer PlatformSummary MP3 BackgroundMP3 NG a Next Generation Consumer Platform Solution OverviewMP3 Technology MP3 NG System Block Diagram IDT RC32364 RISControllerRC32364 Block Diagram RC32364 Read Timing CS4343 Block Diagram Crystal CS4343 Stereo DACControl Port Timing KM29U64000T Block Diagram Samsung Flash MemoryMicron Sdram Memory KM29U64000T Read TimingMT48LC1M16A1 Block Diagram National Semiconductor Function ControllerSystem Implementation Software ArchitectureUI Manager MP3 Decoder and Audio ISRBlock Mapping Xilinx SpartanMemory Manager Code InitializationFpga Logic Block Diagram IP Bus ControllerCPU Interface Block Diagram CPU InterfaceLCD Controller CpumasterclkLCD Controller Block Diagram LCD Controller Interface Signal SummaryMemory Interface Block Diagram Memory InterfaceFlash Controller Sdram Controller Interface Signal Summary Type DescriptionSdram Controller Error Handling PerformanceIrda Controller Block Diagram Irda ControllerAudio DAC Interface Block Diagram Audio DAC InterfaceAudio DAC Interface Signal Summary Type Description Touch Screen InterfaceTotal 500 137 ConclusionSpartan Device Selection References Revision History Date Version # Revision 11/24/99 Initial release

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.
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