3.7A/D Range and Status Read back Register
The A/D range setting and A/D FIFO status can be read back from this register.
Address: BASE + 8h
Attribute: read only
Data Format:
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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| BASE+8h |
| AD_BUSY | FF_FF | FF_HF | FF_EF | 0 | G2 | G1 | G0 |
| BASE+9h |
| X | X | X | X | X | X | X | X |
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| GC0~GC2: | A/D Range control setting |
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| FF_EF: | ‘0’ means FIFO is empty |
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| FF_HF: | ‘0’ means FIFO is |
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| FF_FF: | ‘0’ means FIFO is full, A/D data may have been loss | ||||||||
| AD_BUSY: | ‘0’ means AD is busy, the A/D data has not been latched | ||||||||
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| in FIFO yet. If AD_BUSY changes from ‘0’ to ‘1’, A/D is | |||||||
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| not busy and the data is written into FIFO. |
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3.8A/D Trigger Mode Control Register
This register is used to control the A/D trigger source and trigger method.
Address: BASE + 0Ah
Attribute: write only
Data Format:
Bit | 7 | 6 | 5 | 4 |
| 3 |
| 2 | 1 | 0 |
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BASE+0Ah | X | X | X | X |
| PTRG |
| EITS | TPST | ASCAN |
BASE+0Bh | X | X | X | X |
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| X | X | X |
PTRG: |
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| 0: |
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| 1: |
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EITS: | External / Internal Trigger Source |
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| 1: External Trigger Source |
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| 0: Internal Trigger Source |
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TPST: | Timer Pacer/ Software Trigger |
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| 0: Software Trigger |
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| 1: Timer Pacer Trigger |
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