HP NuDAQ I-9111DG/HR manual Pre-Trigger Control, EOC Interrupt Transfer

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EOC Interrupt Transfer

The PCI-9111 provides traditional hardware end-of-conversion (EOC) interrupt capability. Under this mode, an interrupt signal is generated when the A/D conversion is ended and the data is ready to be read in the FIFO. It is useful to combine the EOC interrupt transfer with the timer pacer trigger mode. After A/D conversion is completed, the hardware interrupt will be inserted and its corresponding ISR (Interrupt Service Routine) will be invoked and executed. The converted data can be read by the ISR program. This method is most suitable for data processing applications under real-time and fixed sampling rate.

FIFO Half-Full Interrupt Transfer

Sometimes, the applications do not need real -time processing, but the foreground program is too busy to poll the FIFO data, then the FIFO half-full interrupt transfer mode is useful. In addition, as the external A/D trigger source is used, the sampling rate may not be easy to predict, then the method could be applied because the CPU only be interrupted when the FIFO is half-full, thus reserved the CPU load.

Under this mode, an interrupt signal is generated when FIFO become half-full, that means there are 512 words data in the FIFO already. The ISR can read a block of data at every interrupt occurring. This method is very convenient to read A/D in size of a “block” (512 words) and it is benefit for software programming.

4.1.5Pre-Trigger Control

In certain applications, the data acquisition is applied and stops under special hardware signal. Without Pre-Trigger function, the software can start the A/D at any time, but it is very difficult to stop the A/D in real-time by software. Under “Pre-Trigger” mode, the pre-trigger (PTRG) signal (from pin-12 of CN3) and the 8254 counter 0 are used to “STOP” the A/D sampling.

After setting up the Pre-Trigger mode, the hardware is continuously acquiring A/D data and waiting for the pre-trigger signal. Before the pre-trigger signal is inserted, the software must read the FIFO data to prevent FIFO full. Besides, if these data are usable, the software should store these data as many as possible to the host PC‘s memory.

When the pre-trigger signal is inserted, the counter is starting to count down from the initial counter value N to count the number of the A/D conversion trigger signal. The A/D trigger will be disabled automatically when the counter value reach zero. The value of N could be 1 to 65535 and the last N A/D data is sampled after the pre-trigger signal. The

28 ∙ Operation Theorem

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Contents NuDAQ Trademarks Getting service from Adlink QuestionsPage PCI PnP Registers Address Map Features Applications Specifications Software SupportingB l e o f C o n t e n t s Conversion Libraries Installation Programming GuideHardware Interrupt Clear Register Interrupt ControlTable of Contents ∙ What do you need VR Assignment Adjustment 9111utilHow to Use This Guide Page Features IntroductionSpecifications ApplicationsUnipolar 0~10V Bipolar -10V~+10V Software Supporting Programming LibraryDAQBenchTM ActiveX Controls PCIS-LVIEW LabVIEW DriverPCIS-VEE HP-VEE Driver DASYLabTM PROPCIS-ICL InControlTM Driver PCIS-OPC OPC ServerWhat You Have Installation∙ Software Installation Guide UnpackingPCI-9111s Layout PCB Layout of the PCI-9111Hardware Installation Outline Jumper Descriptions∙ CN 1 Digital Signal Input DI 0 ~ Device Installation for Windows SystemsConnectors Pin Assignment ∙ CN 2 Digital Signal Output do 0 ~ ∙ CN 3 Analog Input/Output, Extended I/O, Trigger SignalsConnect with ACLD-9137 Daughter Board ConnectionConnect with ACLD-8125 Connect with ACLD-9182Registers Format PCI PnP RegistersAddress Write Read I/O Address MapA/D Data Registers I/O AddressBit A/D Channel Control RegisterAddress Base + 0h Attribute read only Data Format Address Base + 6h Attribute write only Data Format BitAddress Base + 6h Attribute read only Data Format Bit A/D Input Signal Range Control RegisterA/D Channel Read Back Register Address Base + 8h Attribute write only Data Format BitAddress Base + 8h Attribute read only Data Format Bit A/D Trigger Mode Control RegisterA/D Range and Status Read back Register Address Base + 0Ah Attribute write only Data Format BitAddress Base + 0Ch Attribute write only Data Format Bit Mode DescriptionAddress Base + 0Eh Attribute write only Data Format Bit Address Base + 48h Attribute write only Data Format Bit 12 A/D Mode & Interrupt Control Read Back RegisterHardware Interrupt Clear Register Address Base + 0Ah Attribute read only Data Format BitAddress Base + 2h Attribute read only Data Format Address Base + 4h Attribute write only Data Format BitAddress Base + 4h Attribute read only Data Format Bit Address Base + 40h ~ Base + 46h 15 D/A Output RegisterAddress Base + 2h Attribute write only Data Format Bit Operation Theorem A/D Conversion1 A/D Conversion Procedure 2 A/D Signal Source ControlAnalog Input Signal Connection Signal Range 3 A/D Trigger Source Control4 A/D Data Transfer Modes External Trigger EITS=1, TPST=don‘t careFifo Half-Full Polling Pre-Trigger Control EOC Interrupt TransferTime 6 A/D Data Format FFFDual Interrupt System IRQ Level SettingInterrupt Control System Architecture Interrupt Source Control Extended Digital I/O PortD/A Conversion 44mV 88mVTimer/Counter Operation Introduction Digital Input and Output4 I/O Address Pacer Trigger SourcePre-Trigger Counter Libraries Installation ++ LibraryProgramming Guide Naming Convention Data Types++ DOS 9111Initial9111DO ++ Windows9111DOChannel 9111DI9111DIChannel 9111EDI9111EDO 10 9111EDOReadBack11 9111SetEDOFunction 12 9111DA 13 9111ADReadData14 9111ADReadDataRepeat 15 9111ADSetChannel16 9111ADGetChannel 17 9111ADSetRange Input Range Gain Gain Code18 9111ADGetRange 19 9111ADGetStatus20 9111ADSetMode 21 9111ADGetMode 22 9111INTSetReg24 9111ResetFIFO 23 9111INTGetReg25 9111ADSoftTrigger 26 9111Set825428 9111ADTimer 27 9111Get825429 9111CounterStart 30 9111CounterRead31 9111CounterStop 32 9111INTSourceControl 33 9111CLRIRQ 34 9111GetIRQChannel35 9111GetIRQStatus 36 9111ADFFHFPolling37 9111ADAquire 38 9111ADHRAquire39 9111ADINTStart 40 9111ADFFHFINTStart ++ Library ∙61 41 9111ADINTStatus 42 9111ADFFHFINTStatus43 9111ADFFHFINTRestart 44 9111ADINTStop Calibration What do you needFunctions of VRs A/D AdjustmentVR Assignment D/A Adjustment Unipolar Analog Output Bipolar Analog OutputRunning 9111util.exe Software Utility9111util System Configuration Calibration Functional Testing Function Testing Menu WindowIeeprom Product Warranty/Service
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