HP NuDAQ I-9111DG/HR manual Pacer Trigger Source, Pre-Trigger Counter, 4 I/O Address

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4.6.2Pacer Trigger Source

The timer #1 and timer #2 are cascaded together to generate the timer pacer trigger of A/D conversion. The frequency of the pacer trigger is software controllable. The maximum pacer signal rate is 2MHz/4=500K which excess the maximum A/D conversion rate of the PCI-9111. The minimum signal rate is 2MHz/65535/65535, which is a very slow frequency that user may never use it. The output of the programmable timer can be used as pacer interrupt source or the timer pacer trigger source of A/D conversion. In software library, the timer #1 and #2 are always set as mode 3 (rate generator).

4.6.3Pre-Trigger Counter

The timer #0 is used as the pre-trigger counter. The clock source of counter 0 is from A/D trigger source so that 8254 can count the A/D trigger numbers after the pre-trigger signal (pin-12 of CN3) is inserted. The gate control is set when the pre-trigger signal is change from ‘H’ to ‘L’, and cleared when the counter is counting down to zero. In software library, the timer #0 is always set as mode 0 (event counter).

4.6.4I/O Address

The 8254 in the PCI-9111 occupy 4 I/O address as shown below.

BASE + 40 h	LSB OR MSB OF COUNTER 0
BASE + 42 h	LSB OR MSB OF COUNTER 1
BASE + 44 h	LSB OR MSB OF COUNTER 2
BASE + 46 h	CONTROL BYTE

The programming of 8254 is controlled by the registers BASE+0 to BASE+3. Users can refer to 82C54 data sheet for the descriptions about all the features of 82C54. You can download the data sheet on the following web site:

“http://support.intel.com/support/controllers/peripheral/231164.htm”

or “http://www.tundra.com/”

Operation Theorem ∙35

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Contents NuDAQ Trademarks Questions Getting service from AdlinkPage Features Applications Specifications Software Supporting B l e o f C o n t e n t sPCI PnP Registers Address Map Hardware Interrupt Clear Register Libraries Installation Programming GuideConversion Interrupt ControlTable of Contents ∙ 9111util What do you need VR Assignment AdjustmentHow to Use This Guide Page Introduction FeaturesApplications SpecificationsUnipolar 0~10V Bipolar -10V~+10V Programming Library Software SupportingPCIS-VEE HP-VEE Driver PCIS-LVIEW LabVIEW DriverDAQBenchTM ActiveX Controls DASYLabTM PROPCIS-OPC OPC Server PCIS-ICL InControlTM Driver∙ Software Installation Guide InstallationWhat You Have UnpackingPCB Layout of the PCI-9111 PCI-9111s LayoutJumper Descriptions Hardware Installation OutlineDevice Installation for Windows Systems Connectors Pin Assignment∙ CN 1 Digital Signal Input DI 0 ~ ∙ CN 3 Analog Input/Output, Extended I/O, Trigger Signals ∙ CN 2 Digital Signal Output do 0 ~Connect with ACLD-8125 Daughter Board ConnectionConnect with ACLD-9137 Connect with ACLD-9182PCI PnP Registers Registers FormatA/D Data Registers I/O Address MapAddress Write Read I/O AddressAddress Base + 0h Attribute read only Data Format A/D Channel Control RegisterBit Address Base + 6h Attribute write only Data Format BitA/D Channel Read Back Register A/D Input Signal Range Control RegisterAddress Base + 6h Attribute read only Data Format Bit Address Base + 8h Attribute write only Data Format BitA/D Range and Status Read back Register A/D Trigger Mode Control RegisterAddress Base + 8h Attribute read only Data Format Bit Address Base + 0Ah Attribute write only Data Format BitMode Description Address Base + 0Eh Attribute write only Data Format BitAddress Base + 0Ch Attribute write only Data Format Bit Hardware Interrupt Clear Register 12 A/D Mode & Interrupt Control Read Back RegisterAddress Base + 48h Attribute write only Data Format Bit Address Base + 0Ah Attribute read only Data Format BitAddress Base + 4h Attribute write only Data Format Bit Address Base + 4h Attribute read only Data Format BitAddress Base + 2h Attribute read only Data Format 15 D/A Output Register Address Base + 2h Attribute write only Data Format BitAddress Base + 40h ~ Base + 46h A/D Conversion Operation Theorem2 A/D Signal Source Control 1 A/D Conversion ProcedureAnalog Input Signal Connection 3 A/D Trigger Source Control Signal RangeExternal Trigger EITS=1, TPST=don‘t care 4 A/D Data Transfer ModesFifo Half-Full Polling EOC Interrupt Transfer Pre-Trigger ControlTime FFF 6 A/D Data FormatIRQ Level Setting Interrupt Control System ArchitectureDual Interrupt System Extended Digital I/O Port Interrupt Source Control44mV 88mV D/A ConversionDigital Input and Output Timer/Counter Operation IntroductionPacer Trigger Source Pre-Trigger Counter4 I/O Address ++ Library Libraries InstallationData Types Programming Guide Naming Convention9111DO 9111Initial++ DOS ++ Windows9111DI 9111DOChannel9111EDI 9111DIChannel10 9111EDOReadBack 9111EDO11 9111SetEDOFunction 13 9111ADReadData 12 9111DA15 9111ADSetChannel 14 9111ADReadDataRepeat16 9111ADGetChannel Input Range Gain Gain Code 17 9111ADSetRange19 9111ADGetStatus 18 9111ADGetRange20 9111ADSetMode 22 9111INTSetReg 21 9111ADGetMode23 9111INTGetReg 24 9111ResetFIFO26 9111Set8254 25 9111ADSoftTrigger27 9111Get8254 28 9111ADTimer30 9111CounterRead 29 9111CounterStart31 9111CounterStop 32 9111INTSourceControl 34 9111GetIRQChannel 33 9111CLRIRQ36 9111ADFFHFPolling 35 9111GetIRQStatus38 9111ADHRAquire 37 9111ADAquire39 9111ADINTStart 40 9111ADFFHFINTStart ++ Library ∙61 42 9111ADFFHFINTStatus 41 9111ADINTStatus43 9111ADFFHFINTRestart 44 9111ADINTStop What do you need CalibrationA/D Adjustment VR AssignmentFunctions of VRs Bipolar Analog Output D/A Adjustment Unipolar Analog OutputSoftware Utility 9111utilRunning 9111util.exe System Configuration Calibration Function Testing Menu Window Functional TestingIeeprom Product Warranty/Service