Cypress CY7C1245V18 manuals
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Cypress CY7C1245V18 Manual
28 pages 647.05 Kb
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 36-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)Features Configurations Functional Description Selection Guide 2 CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18Document Number: 001-06365 Rev. *D Page 2 of 28 Logic Block Diagram (CY7C1241V18) Logic Block Diagram (CY7C1256V18) 3 CY7C1243V18, CY7C1245V18Document Number: 001-06365 Rev. *D Page 3 of 28 Logic Block Diagram (CY7C1243V18) Logic Block Diagram (CY7C1245V18) 4 CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18Pin ConfigurationsCY7C1241V18 (4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 5 CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18Pin ConfigurationsCY7C1243V18 (2M x 18) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 6 CY7C1241V18, CY7C1256V187 CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V188 CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18Functional OverviewRead Operations Write Operations Byte Write Operations Concurrent Transactions 9 Depth ExpansionProgrammable Impedance Echo Clocks Valid Data Indicator (QVLD) Delay Lock Loop (DLL) 10 Application ExampleTruth TableSRAM #1 SRAM #4 BUS MASTER (CPU or ASIC) 12 CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V1818 CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18Identification Register Definitions Scan Register Sizes Instruction Codes 19 Boundary Scan Order 20 Power Up Sequence in QDR-II+ SRAMPower Up SequenceClock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) DLL Constraints Power Up WaveformsVDD/VDDQ DOFFUnstable Clock > 2048 Stable Clock Start Normal Operation VDD/VDDQ Stable (< + 0.1V DC per 50 ns) 21 Maximum Ratings Operating Range Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics 22 CapacitanceThermal Resistance AC Test Loads and Waveforms 23 Switching Characteristics 24 CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18Document Number: 001-06365 Rev. *D Page 24 of 28 Switching Waveforms NOPREADFigure 4. Read/Write/Deselect Sequence waveform for 2.0 Cycle Read Latency NOP WRITE READ WRITE 123 4 5 6 78 25 CY7C1241V18, CY7C1256V18
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