Cypress CY7C1256V18, CY7C1241V18 Logic Block Diagram CY7C1243V18, Logic Block Diagram CY7C1245V18

CY7C1241V18, CY7C1256V18

CY7C1243V18, CY7C1245V18

Logic Block Diagram (CY7C1243V18)

						D[17:0]	18
							Address
A(18:0)							Register
					19
			K				CLK
			K
							Gen.
		DOFF
		VREF
	WPS						Control
	BWS						Logic
				[1:0]

	Write	Write	Write		Write
								Address
	Reg	Reg	Reg		Reg			Register
Decode	512K x	512K x	512K x		512K x	Decode
WriteAdd.	18Array	18Array	18Array		18Array	ReadAdd.				Logic
									Control
	Read Data Reg.
			72	36
							Reg.				Reg.
				36
							Reg.

18

19A(18:0)

RPS

CQ

CQ

Q[17:0]

18

QVLD

Logic Block Diagram (CY7C1245V18)

						D[35:0]	36
							Address
A(17:0)							Register
					18
			K				CLK
			K
							Gen.
		DOFF
	VREF
	WPS						Control
	BWS						Logic
				[3:0]

Document Number: 001-06365 Rev. *D

	Write	Write	Write	Write
							Address
	Reg	Reg	Reg	Reg
							Register
Decode	256K x	256K x	256K x	256K x	Decode
WriteAdd.	36Array	36Array	36Array	36Array	ReadAdd.				Logic
								Control
	Read Data Reg.
			144	72
						Reg.				Reg.
			72
						Reg.

36

18A(17:0)

RPS

CQ

CQ

Q[35:0]

36

QVLD

Page 3 of 28

[+] Feedback