Cypress CY7C1241V18, CY7C1243V18, CY7C1245V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Document Number: 001-06365 Rev. *D Page 3 of 28
Logic Block Diagram (CY7C1243V18)
Logic Block Diagram (CY7C1245V18)
512K x 18 Array
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
19
18
72
18
BWS[1:0]
VREF
Write Add. Decode
Write
Reg
36
A(18:0)
19
512K x 18 Array 512K x 18 Array 512K x 18 Array
Write
Reg Write
Reg Write Reg
18
CQ
CQ
DOFF
QVLD
256K x 36 Array
CLK
A(17:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS Q[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
18
36
144
36
BWS[3:0]
VREF
Write Add. Decode
Write
Reg
72
A(17:0)
18
256K x 36 Array 256K x 36 Array 256K x 36 Array
Write
Reg Write
Reg Write Reg
36
CQ
CQ
DOFF
QVLD
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