Contents
Main
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18
36-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Features
Configurations
Functional Description
Selection Guide
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18
Document Number: 001-06365 Rev. *D Page 2 of 28
Logic Block Diagram (CY7C1241V18)
Logic Block Diagram (CY7C1256V18)
CY7C1243V18, CY7C1245V18
Document Number: 001-06365 Rev. *D Page 3 of 28
Logic Block Diagram (CY7C1243V18)
Logic Block Diagram (CY7C1245V18)
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18
Pin Configurations
CY7C1241V18 (4M x 8)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1256V18 (4M x 9)
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18
Pin Configurations
CY7C1243V18 (2M x 18)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1245V18 (1M x 36)
CY7C1241V18, CY7C1256V18
Pin Definitions
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18
NC NC
Pin Definitions
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18
Functional Overview
Read Operations
Write Operations
Byte Write Operations
Depth Expansion
Programmable Impedance
Echo Clocks
Valid Data Indicator (QVLD)
Delay Lock Loop (DLL)
Application Example
Truth Table
SRAM #1
SRAM #4
BUS MASTER (CPU or ASIC)
Page
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18
IEEE 1149.1 Serial Boundary Scan (JTAG)
Disabling the JTAG Feature
Test Access Port Test Clock
Test Mode Select
Test Data-In (TDI)
Page
TAP Controller State Diagram
TAP Controller Block Diagram
TAP Electrical Characteristics
TAP AC Switching Characteristics
TAP Timing and Test Conditions
Test Clock Test Mode Select
TCK TMS Test Data In TDI Test Data Out
TDO
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18
Identification Register Definitions
Scan Register Sizes
Instruction Codes
Boundary Scan Order
Power Up Sequence in QDR-II+ SRAM
Power Up Sequence
Clock Start (Clock Starts after VDD/VDDQ is Stable)
Fix HIGH (tie to VDDQ)
DLL Constraints
Maximum Ratings
Operating Range
Electrical Characteristics
DC Electrical Characteristics
AC Electrical Characteristics
Capacitance
Thermal Resistance
AC Test Loads and Waveforms
Switching Characteristics
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18
Document Number: 001-06365 Rev. *D Page 24 of 28
Switching Waveforms
QVLD
RPS
CY7C1241V18, CY7C1256V18
Ordering Information
Document Number: 001-06365 Rev. *D Page 27 of 28
Package Diagram
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Figure 5. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195
51-85195-*A
Document History Page