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Cypress CY7C1245V18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

Models: CY7C1241V18 CY7C1245V18 CY7C1256V18 CY7C1243V18

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CY7C1241V18, CY7C1256V18

CY7C1243V18, CY7C1245V18

Identification Register Definitions

	Instruction		Value			Description
	Field	CY7C1241V18	CY7C1256V18	CY7C1243V18	CY7C1245V18	Description
	Field	CY7C1241V18	CY7C1256V18	CY7C1243V18	CY7C1245V18
	Revision	000	000	000	000	Version number.
	Number (31:29)
	Cypress Device	11010010101000111	11010010101001111	11010010101010111	11010010101100111	Defines the type
	ID (28:12)					of SRAM.
	Cypress JEDEC	00000110100	00000110100	00000110100	00000110100	Enables unique
	ID (11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an
						ID register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	109

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input/output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between
		TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input/output contents. Places the boundary scan register between
		TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input/output ring contents. Places the boundary scan register
		between TDI and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect
		SRAM operation.

Document Number: 001-06365 Rev. *D

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Cypress CY7C1245V18 Identification Register Definitions, Scan Register Sizes, Instruction Codes, Register Name Bit Size

Contents

Functional Description FeaturesConfigurations Selection Guide Logic Block Diagram CY7C1241V18 Logic Block Diagram CY7C1256V18Doff Logic Block Diagram CY7C1243V18 Logic Block Diagram CY7C1245V18 CY7C1256V18 4M x Pin ConfigurationsCY7C1241V18 4M x NC/144M CY7C1243V18 2M x CY7C1245V18 1M xWPS BWS RPS Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for Jtag Byte Write Operations Functional OverviewWrite Operations Read Operations Depth Expansion Valid Data Indicator QvldDelay Lock Loop DLL Programmable Impedance Sram #4 Application ExampleTruth Table BUS Master Remains unaltered Write Cycle DescriptionsComments During the data portion of a write sequence Written into the device. D 359 remains unaltered Write cycle description table for CY7C1245V18 follows.2Into the device Into the device. D 80 and D 3518 remain unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max Unit TAP AC Switching Characteristics TAP Timing and Test Conditions16 Instruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit Size Boundary Scan Order Bit # Bump ID Power Up Waveforms Power Up Sequence in QDR-II+ SramPower Up Sequence DLL Constraints AC Electrical Characteristics Electrical CharacteristicsDC Electrical Characteristics Maximum Ratings AC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max Unit Parameter Min Max Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Set-up Times Switching Waveforms NOP Read Write Ordering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Package Diagram Ball Fbga 15 x 17 x 1.40 mm VKN/KKVTMP Document HistoryNXR VKN/AESA