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Cypress CY7C1241V18, CY7C1243V18, CY7C1245V18, CY7C1256V18 CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

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CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18

Document Number: 001-06365 Rev. *D Page 24 of 28

Switching Waveforms

Figure 4. Read/Write/Deselect Sequence waveform for 2.0 Cycle Read Latency[30, 31, 32]

tKH tKL tCYC tKHKH

NOPREAD

NOP WRITE READ WRITE

123 4 5 6 78

tSA HA

SC HC

tHD

tSC tHC

A0 A1 A2 A3

tSD

D11D10 D12 D13 D30 D31 D32 D33

D

A

WPS

RPS

DON’T CARE UNDEFINED

CQ

tCQOH

CCQO

tCQOH

CCQO

tQVLD

QVLD

tQVLD

(Read Latency = 2.0 Cycles)

CLZ

tCO

tDOH tCQDOH

CQD

ttCHZ

Q00 Q01 Q20

Q02 Q21

Q03 Q22 Q23

tCQH t

CQHCQH

Q

Notes

30.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.

31.Outputs are disabled (High-Z) one clock cycle after a NOP.

32.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole

diagram.

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Contents

Main CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 36-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Functional Description Selection Guide CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 2 of 28 Logic Block Diagram (CY7C1241V18) Logic Block Diagram (CY7C1256V18) CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 3 of 28 Logic Block Diagram (CY7C1243V18) Logic Block Diagram (CY7C1245V18) CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Pin Configurations CY7C1241V18 (4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1256V18 (4M x 9) CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Pin Configurations CY7C1243V18 (2M x 18) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1245V18 (1M x 36) CY7C1241V18, CY7C1256V18 Pin Definitions CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 NC NC Pin Definitions CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Functional Overview Read Operations Write Operations Byte Write Operations Depth Expansion Programmable Impedance Echo Clocks Valid Data Indicator (QVLD) Delay Lock Loop (DLL) Application Example Truth Table SRAM #1 SRAM #4 BUS MASTER (CPU or ASIC) Page CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access Port Test Clock Test Mode Select Test Data-In (TDI) Page TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Test Clock Test Mode Select TCK TMS Test Data In TDI Test Data Out TDO CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Identification Register Definitions Scan Register Sizes Instruction Codes Boundary Scan Order Power Up Sequence in QDR-II+ SRAM Power Up Sequence Clock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) DLL Constraints Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev. *D Page 24 of 28 Switching Waveforms QVLD RPS CY7C1241V18, CY7C1256V18 Ordering Information Document Number: 001-06365 Rev. *D Page 27 of 28 Package Diagram [+] Feedback [+] Feedback Figure 5. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 51-85195-*A Document History Page