CY7C1241V18, CY7C1256V18CY7C1243V18, CY7C1245V18
Document Number: 001-06365 Rev. *D Page 24 of 28

Switching Waveforms

Figure 4. Read/Write/Deselect Sequence waveform for 2.0 Cycle Read Latency[30, 31, 32]
tKH tKL tCYC tKHKH

NOPREAD

NOP WRITE READ WRITE

123 4 5 6 78

t
t
t
tSA HA
SC HC
tHD
tSC tHC
A0 A1 A2 A3
t
t
SD
HD
tSD
D11D10 D12 D13 D30 D31 D32 D33
D
A
WPS
RPS
K
K
DON’T CARE UNDEFINED
CQ
CQ
tCQOH
CCQO
t
tCQOH
CCQO
t
tQVLD
QVLD
tQVLD
(Read Latency = 2.0 Cycles)
CLZ
t
tCO
tDOH tCQDOH
CQD
ttCHZ
Q00 Q01 Q20
Q02 Q21
Q03 Q22 Q23
tCQH t
CQHCQH
Q
Notes
30.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
31.Outputs are disabled (High-Z) one clock cycle after a NOP.
32.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole
diagram.
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