Cypress CY7C1241V18, CY7C1243V18 Functional Overview, Byte Write Operations, Read Operations

CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

Functional Overview

The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are synchronous pipelined Burst SRAMs equipped with a read and a write port. The read port is dedicated to read operations and the write port is dedicated to write opera- tions. Data flows into the SRAM through the write port and out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR-II+ completely eliminates the need to “turn around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1241V18, four 9-bit data transfers in the case of CY7C1256V18, four 18-bit data transfers in the case of CY7C1243V18, and four 36-bit data transfers in the case of CY7C1245V18, in two clock cycles.

Accesses for both ports are initiated on the Positive Input Clock

(K). All synchronous input and output timing refer to the rising edge of the input clocks (K/K).

All synchronous data inputs (D[x:0]) inputs pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) outputs pass through output registers controlled by the rising edge of the Input clocks (K and K).

All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K/K).

CY7C1243V18 is described in the following sections. The same basic descriptions apply to CY7C1241V18, CY7C1256V18, and CY7C1245V18.

Write Operations

Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the following K clock rise, the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K), the information presented to D[17:0] is also stored into the Write Data register, provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, write accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second write request. Write accesses can be initiated on every other rising edge of the Positive Input Clock

(K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K).

When deselected, the write port ignores all inputs after the pending write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1243V18. A Write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and written into the device. Deasserting the Byte Write Select input during the data portion of a write allows the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read/modify/write operations to a Byte Write operation.

Read Operations

The CY7C1243V18 is organized internally as 4 arrays of 512K x

18.Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The addresses presented to Address inputs are stored in the Read address register. Following the next two K clock rising edges, the corresponding lowest order 18-bit word of data is driven onto the

Q[17:0] using K as the output timing reference. On the subse- quent rising edge of K the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data words have been driven out onto Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the input clock (K or K). To maintain the internal logic, each read access must be allowed to complete. Each read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, read accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second read request. Read accesses can be initiated on every other K clock rise. Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks (K and K).

When the read port is deselected, the CY7C1243V18 first completes the pending Read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the Positive Input Clock (K). This enables a seamless transition between devices without the insertion of wait states in a depth expanded memory.

Concurrent Transactions

The read and write ports on the CY7C1243V18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, you can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise.

Read accesses and write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the read port takes priority. If a read was initiated on the previous cycle, the write port assumes priority (because read operations cannot be initiated on consecutive cycles). If a write was initiated on the previous cycle, the Read port assumes priority (because write operations cannot be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alternating read/write operations being initiated, with the first access being a read.

Document Number: 001-06365 Rev. *D Page 8 of 28

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