Cypress CY7C1241V18, CY7C1243V18, CY7C1245V18, CY7C1256V18 CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Document Number: 001-06365 Rev. *D Page 2 of 28
Logic Block Diagram (CY7C1241V18)
Logic Block Diagram (CY7C1256V18)
1M x 8 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS Q[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
20
8
32
8
NWS[1:0]
VREF
Write Add. Decode
Write
Reg
16
A(19:0)
20
1M x 8 Array 1M x 8 Array 1M x 8 Array
Write
Reg Write
Reg Write Reg
8
CQ
CQ
DOFF
QVLD
1M x 9 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS Q[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
20
9
36
9
BWS[0]
VREF
Write Add. Decode
Write
Reg
18
A(19:0)
20
1M x 9 Array 1M x 9 Array 1M x 9 Array
Write
Reg Write
Reg Write Reg
9
CQ
CQ
DOFF
QVLD
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