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Cypress CY7C1243V18, CY7C1241V18, CY7C1245V18, CY7C1256V18 manual Ordering Information

Models: CY7C1241V18 CY7C1245V18 CY7C1256V18 CY7C1243V18

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CY7C1241V18, CY7C1256V18

CY7C1243V18, CY7C1245V18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
375	CY7C1241V18-375BZC	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1256V18-375BZC

	CY7C1243V18-375BZC

	CY7C1245V18-375BZC

	CY7C1241V18-375BZXC	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1256V18-375BZXC

	CY7C1243V18-375BZXC

	CY7C1245V18-375BZXC

	CY7C1241V18-375BZI	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1256V18-375BZI

	CY7C1243V18-375BZI

	CY7C1245V18-375BZI

	CY7C1241V18-375BZXI	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1256V18-375BZXI

	CY7C1243V18-375BZXI

	CY7C1245V18-375BZXI

333	CY7C1241V18-333BZC	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1256V18-333BZC

	CY7C1243V18-333BZC

	CY7C1245V18-333BZC

	CY7C1241V18-333BZXC	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1256V18-333BZXC

	CY7C1243V18-333BZXC

	CY7C1245V18-333BZXC

	CY7C1241V18-333BZI	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1256V18-333BZI

	CY7C1243V18-333BZI

	CY7C1245V18-333BZI

	CY7C1241V18-333BZXI	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1256V18-333BZXI

	CY7C1243V18-333BZXI

	CY7C1245V18-333BZXI

Document Number: 001-06365 Rev. *D

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Cypress CY7C1243V18, CY7C1241V18, CY7C1245V18, CY7C1256V18 manual Ordering Information

Contents

Configurations FeaturesFunctional Description Selection Guide Logic Block Diagram CY7C1256V18 Logic Block Diagram CY7C1241V18Doff Logic Block Diagram CY7C1245V18 Logic Block Diagram CY7C1243V18 CY7C1241V18 4M x Pin ConfigurationsCY7C1256V18 4M x NC/144M CY7C1245V18 1M x CY7C1243V18 2M xWPS BWS RPS Pin Name Pin Description Pin DefinitionsNegative Input Clock Input Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for Jtag Write Operations Functional OverviewByte Write Operations Read Operations Delay Lock Loop DLL Valid Data Indicator QvldDepth Expansion Programmable Impedance Truth Table Application ExampleSram #4 BUS Master Comments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequence Into the device Write cycle description table for CY7C1245V18 follows.2Written into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max Unit TAP Timing and Test Conditions16 TAP AC Switching Characteristics Scan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit Size Bit # Bump ID Boundary Scan Order Power Up Sequence Power Up Sequence in QDR-II+ SramPower Up Waveforms DLL Constraints DC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum Ratings Thermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max Unit Cypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max Set-up Times NOP Read Write Switching Waveforms Ordering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Ball Fbga 15 x 17 x 1.40 mm Package Diagram NXR Document HistoryVKN/KKVTMP VKN/AESA