Mitel MT90840 manuals

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Features
Applications
Distributed Hyperchannel Switch
- 2Figure 2 - Pin Connections
- 84 PIN PLCC
- 3Pin Description
4MT90840
- Pin Description (continued)
  - Test-Logic-Reset
- 5V
- Pin Description (continued)
- 6Functional Description
- Device Operation
  - 7Figure 3 - Serial Port Interface Functional Timing
  - Figure 4 - Parallel Data Port Functional Timing
8MT90840
- Transmit Path Connection Memory
- Transmit Path Data Memory
- Receive Path Connection Memory
- Receive Path Data Memory
- Bypass
- Parallel Switching
- 9Preliminary Information MT90840
  - 2.048 Mbps Balanced Mode
  - 2.048 Mbps Add/Drop Mode
  - 4.096 Mbps Mode
  - 8.192 Mbps Mode
  - Serial Port Clock Signals
  - Internal 4.096 MHz Clock Generator
  - 10Serial Frame Pulse
  - Parallel Port Clock Signals and Framing
  - 11Timing and Switching Control
    - Asynchronous Parallel Port With ST-BUS Clock Master
    - 12TM1 Multiple-MT90840 Sub-Mode (PFDI)
    - Asynchronous Parallel Port With ST-BUS Clock Slave
    - 13Internal 4.096 MHz Clock Divider
    - External PLL and C4 Phase-Correction
    - TM2 Multiple-MT90840 Sub-Mode (SFDI)
    - 14Synchronous Parallel Port With ST-BUS Clock Slave
  - 15MT90840 Throughput Delay
  - MT90840 Per-channel Functions
    - Per-channel Bypass on the Parallel Port
    - Per-channel Control Outputs on the Parallel Port
17. . . . .
- Per-channel Tri-state (Serial and Parallel)
- Per-channel Message Mode (Serial and Parallel)
- Per-channel Direction Control on the Serial Port
- 18Serial Data Memory Addressing
  - 2.048 Mbps Balanced Mode
  - 2.048 Mbps Add/Drop Mode
  - 194.096 Mbps Mode
  - 8.192 Mbps Mode
- 20Microprocessor Port
  - 21CPU Memory Read Operation
  - CPU Memory Write Operation (Write Pipeline)
  - DTA Operation and TDM Clocks
  - 22Detecting Clock Presence
  - Clock Quality and TM1 TPCM Access Integrity
  - Clock Quality and TM2 RPCM Access Integrity
- 23JTAG Support
  - 24Test Access Port (TAP)
  - Test-Logic-Reset
  - Boundary-Scan Instruction Register
  - 25Test Data Registers
- 26Register Description
  - Interface Mode Selection Register (IMS) - READ/WRITE
    - 0
    - TM1 TM0 C4/8R TCP INTCLK SFDI PFDI
  - DR1
  - Timing Mode Register (TIM) - READ/WRITE
  - 27General Purpose Mode Register (GPM) - READ/WRITE
    - BPD6 BPD5 BPD4 PPFP SPFPBPD7 DIN BPE
    - MSK2 MSK1 MSK0 PPCE TXPAAMSK3 RXPAA FSA
  - Alarm Status Register (ALS) - READ/WRITE
  - 28Control Register (CR) - READ/WRITE
    - SEL1 SEL0 HA11 HA10 HA8SEL2 HA9 HA7
    - 0 0 0 0 PSD9PSD10 PSD8
    - 0
  - Phase Status Registers (PSD) - READ Only
    - PSD6 PSD5 PSD4 PSD3 PSD1PSD7 PSD2 PSD0
    - Register Address 8 (Low Byte) Register Address 9 (High 3-bits)
- 29Internal Memory Description
  - Transmit Path Connection Memory High (TPCM High) -This is an 8-bit x 2430-position memory.
    - AB6 AB5 AB4 AB3 AB1AB7 AB2 AB0 (TX Path CM Low)
    - PPBY MC CTo1 CTo2/ AB9
    - OE/ AB8 CTo0 AB11 CTo3/ AB10 (TX Path CM High)
  - Transmit Path Connection Memory Low (TPCM Low) -This is an 8-bit x 2430-position memory.
  - 30Receive Path Connection Memory High (RPCM High) - This is a 7-bit x 512-position memory.
    - MC DC OE AB11 AB9- AB10 AB8 (RX Path CM High)
  - Used only in TM1, 2 &3.
    - AB6 AB5 AB4 AB3 AB1AB7 AB2 AB0 (RX Path CM Low)
  - Used only in TM1, 2, & 3.
  - Receive Path Connection Memory Low (RPCM Low)- This is an 8-bit x 512-position memor y.
- 31Applications
- 32Absolute Maximum Ratings*
- Recommended Operating Conditions
- DC Electrical Characteristics
- 34AC Electrical Characteristics
  - 35Figure 18 - Serial Port Timing for 2.048 Mbps Operation - TM2 (SFDi = 1) and TM1
  - 36Figure 19 - Serial Port Timing for 2.048 Mbps - TM2 (SFDi = 0) and TM3
  - 37Figure 20 - Serial Port Timing for 4.096 Mbps Operation - TM2 (SFDi = 1) and TM1
  - 38Figure 21 - Serial Port Timing for 4.096 Mbps Operation - TM2 (SFDi = 0) and TM3
  - 39Figure 22 - Serial Port Timing for 8.192 Mbps - TM1 and TM2 (SFDi = 1)
  - Figure 23 - Per-Channel Tristate Characteristics at all Data Rates
40MT90840
- Figure 24 - Serial Port Timing for 8.192 Mbps - Timing Modes 2 and 3
- 41Figure 25 - Timing for the Parallel Port External Control Lines CTo0-3
- Figure 26 - TM1 Parallel Port Transmit Timing (TM1 & PFDI = 1, PPFT is an input)
- Figure 27 - Parallel Port Transmit Timing (PFDI = 0, PPFT is an output)
- 42AC Electrical Characteristics - Parallel Data Port
  - 43Figure 29 - Parallel Port in Timing Mode 4
  - Figure 30 - Phase Variation Between C4/8R1 & C4/8R2 and PCKT Inputs for TM1 Operation
  - Figure 31 - Phase Variation Between C4 and PCKR Inputs for TM2 Operation
    - t t
- 44AC Electrical Characteristics- Intel/National- HPC Multiplexed Bus Mode
  - 45Figure 32 - Intel/National Multiplexed Bus Timing
- 46AC Electrical Characteristics - Motorola Multiplexed Bus Mode
  - 47Figure 33 - Motorola Multiplexed Bus Timing
- 48AC Electrical Characteristics - Boundary-Scan Test Port and RESET Pin
  - 49Figure 36 - 84 PLCC Mechanical Drawing
  - Figure 37 - 100 Pin PQF Mechanical Drawing
  - Dim Min Max
    - A
    - D/E
    - D1/E11.150
    - D2/E21.090
    - F
    - G
    - H
    - I
  - Dim Min Max
    - A
    - b
    - c
    - D
    - E
    - e
    - Hd
    - He
    - L
    - Y